Visible to Intel only — GUID: hco1433527904908
Ixiasoft
1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices
4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices
4.3. Setting Up the Motor Control Board with your Development Board
4.4. Programming the Hardware onto the Device
4.5. Setting Up Terminal Emulator
4.6. Downloading the HPS Software to the Device
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example
6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example
6.3. Vibration Suppression Tab
6.4. Controlling the DC-DC Converter
6.5. Tuning the PI Controller Gains
6.6. Controlling the Speed and Position Demonstrations
6.7. Monitoring Performance
9.1. Processor Subsystem
9.2. Six-channel PWM Interface
9.3. DC Link Monitor
9.4. Drive System Monitor
9.5. Quadrature Encoder Interface
9.6. Sigma-Delta ADC Interface for Drive Axes
9.7. DC-DC Converter
9.8. Motor Control Modes
9.9. FOC Subsystem
9.10. FFTs
9.11. DEKF Technique for Battery Management
9.12. Signals
9.13. Registers
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
9.9.2. Avalon Memory-Mapped Interface
9.9.3. About DSP Builder for Intel FPGAs
9.9.4. DSP Builder for Intel FPGAs Folding
9.9.5. DSP Builder for Intel FPGAs Model Resource Usage
9.9.6. DSP Builder for Intel FPGAs Design Guidelines
9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
Visible to Intel only — GUID: hco1433527904908
Ixiasoft
About the Drive-On-Chip Reference Design
The Drive-On-Chip reference design demonstrates concurrent multiaxis control of up to four three-phase AC 400-V permanent magnet synchronous motors (PMSMs) or sinusoidally wound brushless DC (BLDC) motors.
AC and servo drive system designs comprise multiple distinct but interdependent functions to realize requirements to meet the performance and efficiency demands of modern motor control systems. The system's primary function is to efficiently control the torque and speed of the AC motor through appropriate control of power electronics. A typical drive system includes the following items:
- Flexible pulse-width modulation (PWM) circuitry to switch the power stage transistors appropriately
- Motor control loops for single- or multiaxis control
- Industrial networking interfaces
- Position encoder interfaces
- Current, voltage, and temperature measurement feedback elements.
- Monitoring functions, for example, for vibration suppression.
The system requires system software running on a processor for high-level system control, coordination, and management.
Intel Cyclone® and Intel® MAX® 10 devices offer high-performance fixed- and floating-point DSP functionality. Cyclone V SoC devices offer the integrated ARM-based hard processor subsystem (HPS); other Cyclone FPGA and Intel® MAX® 10 FPGA devices offer support for Nios II soft processors. Cyclone and Intel® MAX® 10 FPGA devices offer a uniquely scalable and flexible platform for integration of single- and multiaxis drives on a single FPGA. The Intel motor control development framework allows you to create these integrated systems easily. The framework provides a reference design that comprises IP cores, software libraries, and a hardware platform. The framework seamlessly integrates Intel system-level design tools such as DSP Builder and Qsys, and software and IP components that allow you to extend and customize the reference design to meet your own application needs. The framework also supports optimal partitioning decisions between software running on an integrated processor and IP performing portions of the motor control algorithm in the FPGA, to accelerate performance as required. For example, depending on the performance requirements of your system or the number of axes you need to support, you may implement all of the inner current control loop in hardware or entirely in software. The framework flexibly allows you to connect to the motor and power stages through off-chip ADCs, and feedback encoder devices and to connect to higher-level automation controllers through off-the-shelf digital encoder and industrial Ethernet IP cores, respectively.
The reference design offers vibration suppression, when you target the Cyclone V SoC devices. The design demonstrates how you can implement standard components (FFTs, FFT-post processing, IIR filter), to enable you to develop an automatic method for vibration suppression. You may use the FFTs and FFT postprocessing for condition monitoring, which detects vibrations that indicate degradation or wear and communicate the results to another system.
The reference design integrates Motor Control IP Suite components, a Nios® II soft processor subsystem, or ARM-based HPS, and software that uses an FOC algorithm. The reference design uses the Intel DSP Builder system-level design tool to implement the FOC algorithm.
DSP Builder provides a MATLAB and Simulink flow that allows you to create hardware optimized fixed latency representations of algorithms without requiring HDL/hardware skills. Intel provides DSP Builder fixed-point and floating point algorithms to demonstrate both options. The DSP Builder folding feature reduces the resource usage of the logic as an alternative to a fully parallel implementation. The reference design also includes an efficient Avalon® Memory-Mapped interface that you can integrate in Qsys.
Related Information