Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

2.3. Intel® Agilex™ M-Series FPGAs and SoCs

Table 12.   Intel® Agilex™ M-Series Device Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device Logic Element Adaptive Logic Module M20K MLAB HBM2E DRAM (GB) DSP Crypto Block
Count Size (Mb) Count Size (Mb) Count 18x19 Multiplier
AGM 032 3,245,000 1,100,000 15,932 311 55,000 33 16 / 32 9,375 18,750
AGM 039 3,851,520 1,305,600 18,960 370 65,280 40 16 / 32 12,300 24,600
Table 13.   Intel® Agilex™ M-Series Device Family Plan—Transceivers and HPSThe values in this table are maximum resources or performance.
Device

CXL* Lane

26

F-Tile R-Tile

HPS

Transceiver Channel

Ethernet Block

30

PCIe* Controller

31

PCIe* 32/

CXL* 35 Controller

FGT 28 FHT 29
32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

AGM 032 1627

64

48

8

8 4 33 4 34 1 Yes
AGM 039 1627

64

48

8

8 4 33 4 34 1 Yes
Table 14.   Intel® Agilex™ M-Series Package with F-TileTable reading example: In package 3184B of AGM 032, there are 720 GPIOs, of which, 360 are LVDS. There are four F-Tiles with FGT channels supporting a maximum total of 64× 32 Gbps NRZ or 48× 58 Gbps PAM4, and FHT channels supporting a maximum total of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4.
Device Package

(Grid Array: Hexagonal)

3184B

(56 mm × 45 mm)

0.92 mm pitch

GPIO LVDS F-Tile ×4
FGT FHT
32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

AGM 032 720 360 64 48 8 8
AGM 039 720 360 64 48 8 8
Table 15.   Intel® Agilex™ M-Series Package with F-Tile and R-TileTable reading example: In package 3687A of AGM 032, there are 768 GPIOs, of which, 384 are LVDS. There are three F-Tiles with FGT channels supporting a maximum of 48× 32 Gbps NRZ or 36× 58 Gbps PAM4, and FHT channels supporting a maximum of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4. There is one R-Tile supporting a maximum of 16× PCIe* at up to 32 Gbps per lane, or 16× CXL* lanes.
Device Package

(Grid Array: Hexagonal)

3687A

(56 mm × 52.5 mm)

0.92 mm pitch

GPIO LVDS F-Tile ×3 R-Tile ×1
FGT FHT 32 Gbps

PCIe*

CXL*
32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

AGM 032 768 384 48 36 8 8 16 16
AGM 039 768 384 48 36 8 8 16 16
Table 16.   Intel® Agilex™ M-Series Package with F-Tile and HBM2ETable reading example: In package 4700B of AGM 032, there are 768 GPIOs, of which, 384 are LVDS. There are three F-Tiles with FGT channels supporting a maximum total of 64× 32 Gbps NRZ or 48× 58 Gbps PAM4, and FHT channels supporting a maximum total of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4. The devices are available with 16 GB or 32 GB in-package HBM2E memory.
Device Package

(Grid Array: Hexagonal)

4700B

(56 mm × 66 mm)

0.92 mm pitch

GPIO LVDS F-Tile ×3 HBM2E (GB)
FGT FHT
32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

AGM 032 768 384 64 48 8 8 16 / 32
AGM 039 768 384 64 48 8 8 16 / 32
Table 17.   Intel® Agilex™ M-Series Package with F-Tile, R-Tile, and HBM2ETable reading example: In package 4700A of AGM 032, there are 768 GPIOs, of which, 384 are LVDS. There are three F-Tiles with FGT channels supporting a maximum of 48× 32 Gbps NRZ or 36× 58 Gbps PAM4, and FHT channels supporting a maximum of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4. There is one R-Tile supporting a maximum of 16× PCIe* at up to 32 Gbps per lane. The devices are available with 16 GB or 32 GB in-package HBM2E memory.
Device Package

(Grid Array: Hexagonal)

4700A

(56 mm × 66 mm)

0.92 mm pitch

GPIO LVDS F-Tile ×3 R-Tile ×1 HBM2E (GB)
FGT FHT 32 Gbps

PCIe*

CXL*
32 Gbps

NRZ

58 Gbps

PAM4

58 Gbps

NRZ

116 Gbps

PAM4

AGM 032 768 384 48 36 8 8 16 16 16 / 32
AGM 039 768 384 48 36 8 8 16 16 16 / 32
26 Maximum CXL* lanes for Intel® Xeon® Scalable Processor.
27 Available in package 3687A.
28 Maximum F-Tile general purpose transceiver (FGT) RS and KP FEC NRZ up to 32 Gbps, or PAM4 up to 58 Gbps.
29 Maximum F-Tile high speed transceiver (FHT) RS and KP FEC NRZ up to 58 Gbps, or PAM4 up to 116 Gbps.
30 Maximum 10, 25, 40, 50, 100, 200, or 400 GbE MAC and FEC hard IP blocks.
31 Maximum PCIe* hard IP blocks ( PCIe* 4.0 ×16) or bifurcatable two PCIe* 4.0 ×8 (EP) or four PCIe* 4.0 ×4 (RP).
32 Maximum PCIe* hard IP blocks ( PCIe* 5.0 ×16) or bifurcatable two PCIe* 5.0 ×8 (EP) or four PCIe* 5.0 ×4 (RP).
33 Maximum of four F-Tiles in package 3184B.
34 Maximum of four PCIe* controllers in package 3184B.
35 Maximum CXL* hard IP blocks ( PCIe* 5.0 ×16) endpoint.

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