Agilex™ 7 FPGAs and SoCs Device Overview

Download PDF
ID 683458
Date 3/18/2025
Public

Visible to Intel only — GUID: ifq1629733962454

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 7 FPGAs and SoCs 2. Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs 18. Device Security for Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs 20. Power Management for Agilex™ 7 FPGAs and SoCs 21. Software and Tools for Agilex™ 7 FPGAs and SoCs 22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 7 FPGAs and SoCs 1.2. Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 7 SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Agilex™ 7 FPGAs and SoCs F-Series 2.2. Agilex™ 7 FPGAs and SoCs I-Series 2.3. Agilex™ 7 FPGAs and SoCs M-Series 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview

2.2. Intel® Agilex™ I-Series FPGAs and SoCs

Table 8.   Intel® Agilex™ I-Series Device Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device Logic Element Adaptive Logic Module eSRAM M20K MLAB DSP Crypto Block
Count Size (Mb) Count Size (Mb) Count Size (Mb) Count 18x19 Multiplier
AGI 019 1,918,975 650,500 1 18 8,500 166 35,525 20 1,354 2,708 2
AGI 023 2,308,080 782,400 1 18 10,464 204 39,120 24 1,640 3,280 2
AGI 022 2,208,075 748,500 — — 10,900 212 37,425 23 6,250 12,500 —
AGI 027 2,692,760 912,800 — — 13,272 259 45,640 28 8,528 17,056 —
AGI 035 3,540,000 1,200,000 3 54 14,931 292 60,000 37 9,594 19,188 4
AGI 040 4,047,400 1,372,000 3 54 19,908 389 68,600 42 12,792 25,584 4
Note: Intel® Agilex™ FPGAs and SoCs support PCIe* blocks in tile locations 15A, 14C, and 15C. CXL is supported in tile locations 14C and 15C in the 2957A package only.
Table 9.   Intel® Agilex™ I-Series Device Family Plan—Transceivers and HPSThe values in this table are maximum resources or performance.
Device

CXL* Lane

14

F-Tile R-Tile

HPS
Transceiver Channel

Ethernet Block

17

PCIe* Controller

18

PCIe* 19/

CXL* 24 Controller

FGT 15

FHT 16

32 Gbps

NRZ

 58 Gbps

PAM4

 58 Gbps

NRZ

 116 Gbps

PAM4
AGI 019 16

64

 48

8

 8 4 20 4 22 1 Yes
AGI 023 16

64

 48

8

 8 4 20 4 22 1 Yes
AGI 022 32

64

 48

8

 8 4 20 4 22 3 Yes
AGI 027 32

64

 48

8

 8 4 20 4 22 3 Yes
AGI 035 —

96

 72

24

 24 6 21 6 23 — —
AGI 040 —

96

 72

24

 24 6 21 6 23 — —
Table 10.   Intel® Agilex™ I-Series Packages with F-TileTable reading example: In package 3184B of AGI 022, there are 720 GPIOs, of which, 360 are LVDS. There are four F-Tiles with FGT channels supporting a maximum total of 64× 32 Gbps NRZ or 48× 58 Gbps PAM4, and FHT channels supporting a maximum total of 8× 58 Gbps NRZ or 8× 116 Gbps PAM4.
Device Package

(Grid Array: Hexagonal)
3184B

(56 mm × 45 mm)

0.92 mm pitch

 3948A

(56 mm × 56 mm)

0.92 mm pitch
GPIO LVDS F-Tile ×4 GPIO LVDS F-Tile ×6
FGT FHT FGT FHT
32 Gbps

NRZ

58 Gbps

PAM4

 58 Gbps

NRZ

116 Gbps

PAM4

 32 Gbps

NRZ

58 Gbps

PAM4

 58 Gbps

NRZ

116 Gbps

PAM4
AGI 019 480 240 64 48 8 8 — — — — — —
AGI 023 480 240 64 48 8 8 — — — — — —
AGI 022 720 360 64 48 8 8 — — — — — —
AGI 027 720 360 64 48 8 8 — — — — — —
AGI 035 — — — — — — 576 288 96 72 24 24
AGI 040 — — — — — — 576 288 96 72 24 24
Table 11.   Intel® Agilex™ I-Series Packages with F-Tile and R-TileTable reading example: In package 2957A of AGI 022, there are 720 GPIOs, of which, 360 are LVDS. There is one F-Tile with FGT channels supporting a maximum of 16× 32 Gbps NRZ or 12× 58 Gbps PAM4, and FHT channels supporting a maximum of 4× 58 Gbps NRZ or 4× 116 Gbps PAM4. There are three R-Tiles supporting a maximum total of 48× PCIe* at up to 32 Gbps per lane, or 32× CXL* lanes.
Device Package

(Grid Array: Hexagonal)
1805A

(42.5 mm × 42.5 mm)

1.025 mm pitch

 2957A

(56 mm × 45 mm)

1.0 or 0.92 mm pitch
GPIO LVDS F-Tile ×1 R-Tile ×1 GPIO LVDS F-Tile ×1 R-Tile ×3
FGT 32 Gbps

PCIe*

FGT FHT 32 Gbps

PCIe*

CXL* 25
32 Gbps

NRZ

58 Gbps

PAM4

 32 Gbps

NRZ

58 Gbps

PAM4

 58 Gbps

NRZ

116 Gbps

PAM4
AGI 019 480 240 16 12 16 — — — — — — — —
AGI 023 480 240 16 12 16 — — — — — — — —
AGI 022 — — — — — 720 360 16 12 4 4 48 32
AGI 027 — — — — — 720 360 16 12 4 4 48 32
14 Maximum CXL* lanes for Intel® Xeon® Scalable Processor.
15 Maximum F-Tile general purpose transceiver (FGT) RS and KP FEC NRZ up to 32 Gbps, or PAM4 up to 58 Gbps.
16 Maximum F-Tile high speed transceiver (FHT) RS and KP FEC NRZ up to 58 Gbps, or PAM4 up to 116 Gbps.
17 Maximum 10, 25, 40, 50, 100, 200, or 400 GbE MAC and FEC hard IP blocks.
18 Maximum PCIe* hard IP blocks ( PCIe* 4.0 ×16) or bifurcatable two PCIe* 4.0 ×8 (EP) or four PCIe* 4.0 ×4 (RP).
19 Maximum PCIe* hard IP blocks ( PCIe* 5.0 ×16) or bifurcatable two PCIe* 5.0 ×8 (EP) or four PCIe* 5.0 ×4 (RP).
20 Maximum of four F-Tiles in package 3184B.
21 Maximum of six F-Tiles in package 3948A.
22 Maximum of four PCIe* controllers in package 3184B.
23 Maximum of six PCIe* controllers in package 3948A.
24 Maximum CXL* hard IP blocks ( PCIe* 5.0 ×16) endpoint.
25 For options to increase available CXL* lanes, contact Intel Premier Support and quote ID #15012021851.
Level Two Title