Intel Agilex® 7 FPGAs and SoCs Device Overview

ID 683458
Date 10/31/2023
Public
Document Table of Contents
Give Feedback

14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs

Select Intel® Agilex™ devices contain multiple instances of the crypto block. The 200 Gbps half-duplex crypto block consists of hardened logic that performs both encryption and decryption functions in a single circuit. The crypto blocks reside in the top and bottom periphery of the device next to the I/O cells.

The crypto block supports these encryption standards:

  • AES standard, used worldwide
  • SM4 standard, used primarily in China

The crypto block supports these different modes of operation:

  • Galois counter mode (GCM)
  • XTS mode, built on top of XOR-encrypt-XOR

The Ethernet MACsec soft IP supports each crypto block, providing a complete MACsec solution for 100 Gbps full-duplex or 200 Gbps half-duplex throughput rates. You can also use the crypto block with a third-party or your own IPsec soft IP.