Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 4/01/2024
Public
Document Table of Contents

1.7. Heterogeneous 3D SiP Transceiver Tile

Intel® Agilex™ FPGAs and SoCs feature power efficient, high bandwidth, low latency transceivers. The transceivers are implemented on heterogeneous 3D System-in-Package (SiP) transceiver tiles. In addition to providing a high-performance transceiver solution to meet current connectivity needs, this allows for future flexibility and scalability as data rates, modulation schemes, and protocol IPs evolve.

Figure 6. Core Fabric and Heterogeneous 3D SiP Transceiver Tiles

There are four types of transceiver tiles available in Intel® Agilex™ FPGAs:

  • E-Tile: General Purpose Transceiver
  • P-Tile: PCIe Gen4 Transceiver
  • F-Tile: General Purpose and PCIe Gen4 Transceiver
  • R-Tile: PCIe Gen5 and Compute Express Link (CXL) Transceiver