Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

1.9. External Memory and General Purpose I/O

Intel® Agilex™ devices offer substantial external memory bandwidth. This bandwidth is provided along with the ease of design, lower power, and resource efficiencies of hardened high-performance memory controllers. The external memory interfaces can be configured up to a maximum width of 72 bits when using either hard or soft memory controllers.

Figure 7. Hard Memory Controller

Each I/O bank contains 96 general purpose I/Os and two high-efficiency hard memory controllers capable of supporting many different memory types, each with different performance capabilities. The hard memory controller is also capable of being bypassed and replaced by a soft controller implemented in the user logic. The I/Os each have a hardened double data rate (DDR) read/write path (PHY) capable of performing key memory interface functionality such as:

  • Read/Write leveling
  • FIFO buffering to lower latency and improve margin
  • Timing calibration
  • On-chip termination

The timing calibration is aided by the inclusion of hard microcontrollers based on Nios® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Intel® Agilex™ device to compensate for any changes in process, voltage, or temperature either within the Intel® Agilex™ device itself or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.

Table 20.  External Memory Interface Performance— Intel® Agilex™ F-Series and I-Series FPGAs
External Memory Interface Memory Controller Type Performance
DDR4 Hard 3,200 Mbps
QDRIV Soft 2,133 Mbps
Table 21.  External Memory Interface Performance— Intel® Agilex™ M-Series FPGAs
External Memory Interface Memory Controller Type Performance
DDR4 Hard 3,200 Mbps
DDR5 Hard 5,600 Mbps
QDRIV Soft 2,133 Mbps
LPDDR5 Hard 5,500 Mbps

Intel® Agilex™ devices also feature general purpose I/Os capable of supporting a wide range of single-ended and differential I/O interfaces, including 1.5 V true differential signaling compatible with LVDS/ RSDS/ Mini-LVDS/ LVPECL. The LVDS compatible solution rates up to 1.6 Gbps are supported.

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