Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 10/31/2023
Public
Document Table of Contents

21.1. Additional SEU Mitigation Features in Intel® Agilex™ D-Series FPGAs and SoCs

Intel® Agilex™ D-Series FPGAs and SoCs also support the following additional SEU mitigation features:

  • Fast SEU detection notification through an IP that connects the LSM pin to the fabric. This notification allows the fabric soft logic to detect reported SEU events faster. You can then retrieve further SEU details through the SDM mailbox.
  • External scrubbing for SEU errors that are not automatically correctable. You can create scrubbing bitstream—up to one sector granularity—to scrub the SEU-corrupted configuration bits while keeping the remaining parts of the device intact.
  • Single-bit ECC injection, ECC error detection, and reporting on memory in the configuration system. You can test the ECC detection logic by issuing ECC injection commands and querying the ECC status from the SDM.