4.1. Design Example Walkthrough
To view the design connections and setup timing for the design example, follow these steps:
- Download the an911_design_examples.par design example from the Intel® FPGA Design Store and restore the design using the Intel® Quartus® Prime Pro Edition software version 23.1.
- At the Intel® Quartus® Prime menu, click and select the top_w2 revision.
- To view the design connections, at the Intel® Quartus® Prime menu, click and select the top_w2.bdf schematic file.
- From the Intel® Quartus® Prime menu, select to compile the project.
You must compile the design to view the setup timing for the design.Once the compilation completes, the Timing Analyzer window displays.
- From the Timing Analyzer menu, select .
- In the Report Timing window, click OK to display the timing report for all paths.