AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel® Agilex™ Devices

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ID 683457
Date 12/20/2022
Public
Document Table of Contents
Document Table of Contents
1. Overview 2. Design Examples Requirements 3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode 4. Using GPIO Intel® FPGA IP in Half-Rate Mode 5. Solutions Comparison 6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel® Agilex™ Devices
1. Overview
1.1. GPIO Intel® FPGA IP Architecture 1.2. Input Data Path Timing Violations
3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode
3.1. Design Example Walkthrough
4. Using GPIO Intel® FPGA IP in Half-Rate Mode
4.1. Design Example Walkthrough
1. Overview
2. Design Examples Requirements
3. Using A Falling Edge Clock for Data Capturing in Full-rate Transfer Mode
4. Using GPIO Intel® FPGA IP in Half-Rate Mode
5. Solutions Comparison
6. Document Revision History for AN 911: Achieving Timing Closure When Using the Top I/O Sub-Bank in Intel® Agilex™ Devices

3.1. Design Example Walkthrough

To view the design connections and setup timing for the design example, follow these steps:

  1. Download the top.par design example from the Design Store for Intel® FPGAs web page and restore the design using the Intel® Quartus® Prime Pro Edition software version 22.3.
  2. At the Intel® Quartus® Prime menu, click Projects > Revisions and select the top_w1 revision.
  3. To view the design connections, at the Intel® Quartus® Prime menu, click File > Open and select the top_w1.bdf schematic file.
  4. From the Intel® Quartus® Prime menu, select Processing > Start Compilation to compile the project.
    You must compile the design to view the setup timing for the design.
    Once the compilation completes, the Timing Analyzer window displays.
  5. From the Timing Analyzer menu, select Reports > Custom Reports > Report Timing.
  6. In the Report Timing window, click OK to display the timing report for all paths.
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