Intel® Quartus® Prime Pro Edition User Guide: Scripting

ID 683432
Date 12/13/2021
Public

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3.1.27.21. set_clock_latency (::quartus::sdc)

The following table displays information for the set_clock_latency Tcl command:

Tcl Package and Version

Belongs to ::quartus::sdc

Syntax set_clock_latency [-h | -help] [-long_help] [-clock <clock_list> ] [-early] [-fall] [-late] [-rise] -source <delay> <targets>
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-clock <clock_list> Valid clock destinations (string patterns are matched using Tcl string matching)
-early Specifies the early clock latency
-fall Specifies the falling transition clock latency
-late Specifies the late clock latency
-rise Specifies the rising transition clock latency
-source Specifies the source clock latency
<delay> Latency delay value
<targets> Valid destinations (string patterns are matched using Tcl string matching)
Description

Specifies clock latency for a given clock or clock target. There are two types of latency: network and source. Network latency is the clock network delay between the clock and register clock pins. Source latency is the clock network delay between the clock and its source (e.g., the system clock or base clock of a generated clock). The Timing Analyzer automatically computes network latencies for all register and generated clocks. Overriding clock network latencies is not supported by the Timing Analyzer. Therefore, the -source option must always be specified. You can apply clock latency to a clock, which affects all targets of the clock, or to a specific clock target. If you specify a specific clock target that is driven by more than one clock, us