Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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6.8.2. Avalon® Streaming RX Status Signals

Table 45.   Avalon® Streaming Interface RX Status Signals
Signal Direction Width Description
avalon_st_rxstatus_valid Out 1

When asserted, this signal qualifies the avalon_st_rxstatus_data[] and avalon_st_rxstatus_error[] signals. The MAC IP core asserts this signal in the same clock cycle the avalon_st_rx_endofpacket signal is asserted.

avalon_st_rxstatus_data[] Out 40

Contains information about the RX frame.

  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame. Ignore this bit when the MAC is configured not to detect stacked VLAN frames (tx_vlan_detection[0] = 1).
  • Bit 33: When set to 1, indicates a VLAN frame. Ignore this bit when the MAC is configured not to detect VLAN frames (tx_vlan_detection[0] = 1).
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_rxstatus_error[] Out 7

When set to 1, the respective bit indicates the following error type in the RX frame.

  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: CRC error.
  • Bit 4: Unused.
  • Bit 5: Unused.
  • Bit 6: PHY error.

The IP core presents the error status on this bus in the same clock cycle it asserts the avalon_st_rxstatus_valid signal. The error status is invalid when an overflow occurs.

avalon_st_rx_pfc_status_valid Out 1

When asserted, this signal qualifies the avalon_st_rx_pfc_status_data[] signal. This signal applies only to 10G operating mode.

avalon_st_rx_pfc_status_data[] Out n

(4 - 16)

n = 2 x Number of PFC queues parameter

When set to 1, the respective bit indicates the flow control request from the remote partner, for example:

  • Bit 0: XON request for priority queue 0.
  • Bit 1: XOFF request for priority queue 0.
  • Bit 2: XON request for priority queue 1.
  • Bit 3: XOFF request for priority queue 1.
  • Bit 4: XON request for priority queue 2.
  • Bit 5: XOFF request for priority queue 2.

When a pair of bits (Example: Bit 0 and Bit 1, Bit 3 and Bit 4, etc.) is set to 0, the respective bit indicates there is no flow control frame sent.

This signal applies only to 10G operating mode.