Intel® Stratix® 10 SX Device Errata

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ID 683399
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Intel® -Specific Errata for the Intel® Stratix® 10 SX Devices 3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata 4. Document Revision History for Intel® Stratix® 10 SX Device Errata
2. Intel® -Specific Errata for the Intel® Stratix® 10 SX Devices x
2.1. FPGA 2.2. Device Power Supply, Core, Configuration and I/O 2.3. Hard Processor System
2.2. Device Power Supply, Core, Configuration and I/O x
2.2.1. M20K Simple Quad-Port Mode Support
2.3. Hard Processor System x
2.3.1. HPS Stops on the First Read Request to SDRAM 2.3.2. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata x
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set 3.2. 845719: A Load May Read Incorrect Data 3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK 3.4. 855872: A Store-Exclusive Instruction May Pass When it Should Fail 3.5. 711668: Configuration Extension Register Has Wrong Value Status 3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 3.7. 855873: An Eviction Might Overtake a Cache Clean Operation 3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output 3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing 3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception 3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results 3.12. 851672: ETM May Trace an Incorrect Exception Address 3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode 3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment 3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address 3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events 3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN 3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
1. About this Document
2. Intel® -Specific Errata for the Intel® Stratix® 10 SX Devices
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata
4. Document Revision History for Intel® Stratix® 10 SX Device Errata

3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata

This section lists the Arm* Cortex-A53 MPCore* and CoreSight* errata.
Note: This errata only applies if you are using devices which are enabled with the Hard Processor System (HPS).
Each listed erratum has an associated category number which identifies the degree of the behavior.

The categories are as follows:

  • Category 1: Behavior has no workaround and severely restricts the use of the product in all, or the majority of applications, rendering the device unusable.
  • Category 2: Behavior contravenes the specified behavior and might limit or severely impair the intended use of the specified features, but does not render the product unusable in all or the majority of applications.
  • Category 3: Behavior that was not the originally intended behavior but should not cause any problems in applications.
Note: This device only contains category 2 and category 3 errata.
Table 2.   Arm* Cortex-A53 MPCore* Processor and CoreSight* Errata
Errata Listing Category Number
843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set

Category 2
845719: A Load May Read Incorrect Data

Category 2
855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK

Category 2
855872: A Store-Exclusive Instruction May Pass When it Should Fail

Category 2
711668: Configuration Extension Register Has Wrong Value Status

Category 3
720107: Periodic Synchronization Can Be Delayed and Cause Overflow

Category 3
855873: An Eviction Might Overtake a Cache Clean Operation

Category 3
853172: ETM May Assert AFREADY Before All Data Has Been Output

Category 3
836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing

Category 3
836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception

Category 3
845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results

Category 3
851672: ETM May Trace an Incorrect Exception Address

Category 3
851871: ETM May Lose Counter Events While Entering WFx Mode

Category 3
852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment

Category 3
852521: A64 Unconditional Branch May Jump to Incorrect Address

Category 3
855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events

Category 3
855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN

Category 3
855830: Loads of Mismatched Size May not be Single-Copy Atomic

Category 3

Section Content
Arm Cortex-A53 MPCore and CoreSight Errata

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