External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.6.2. Timing Analysis Description for Arria 10 EMIF IP

Timing analysis of Arria 10 external memory interface IP is somewhat simpler than that of UniPHY-based IP, because Arria 10 devices have more hardened blocks and there are fewer soft logic registers to be analyzed, because most are user logic registers.

Your Arria 10 EMIF IP includes a Synopsys Design Constraints File (.sdc) which contains timing constraints specific to your IP. The .sdc file also contains Tool Command Language (.tcl) scripts which perform various timing analyses specific to memory interfaces.

Two timing analysis flows are available for Arria 10 EMIF IP:

  • Early I/O Timing Analysis, which is a precompilation flow.
  • Full Timing Analysis, which is a post-compilation flow.

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