External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.5.5.9. Stratix 10 EMIF IP LPDDR3 Parameters: Example Designs

Table 416.  Group: Example Designs / Available Example Designs
Display Name Identifier Description
Select design EX_DESIGN_GUI_LPDDR3_SEL_DESIGN Specifies the creation of a full Quartus Prime project, instantiating an external memory interface and an example traffic generator, according to your parameterization. After the design is created, you can specify the target device and pin location assignments, run a full compilation, verify timing closure, and test the interface on your board using the programming file created by the Quartus Prime assembler. The 'Generate Example Design' button lets you generate simulation or synthesis file sets.
Table 417.  Group: Example Designs / Example Design Files
Display Name Identifier Description
Simulation EX_DESIGN_GUI_LPDDR3_GEN_SIM Specifies that the 'Generate Example Design' button create all necessary file sets for simulation. Expect a short additional delay as the file set is created. If you do not enable this parameter, simulation file sets are not created. Instead, the output directory will contain the ed_sim.qsys file which holds Qsys details of the simulation example design, and a make_sim_design.tcl file with other corresponding tcl files. You can run make_sim_design.tcl from a command line to generate the simulation example design. The generated example designs for various simulators are stored in the /sim sub-directory.
Synthesis EX_DESIGN_GUI_LPDDR3_GEN_SYNTH Specifies that the 'Generate Example Design' button create all necessary file sets for synthesis. Expect a short additional delay as the file set is created. If you do not enable this parameter, synthesis file sets are not created. Instead, the output directory will contain the ed_synth.qsys file which holds Qsys details of the synthesis example design, and a make_qii_design.tcl script with other corresponding tcl files. You can run make_qii_design.tcl from a command line to generate the synthesis example design. The generated example design is stored in the /qii sub-directory.
Table 418.  Group: Example Designs / Generated HDL Format
Display Name Identifier Description
Simulation HDL format EX_DESIGN_GUI_LPDDR3_HDL_FORMAT This option lets you choose the format of HDL in which generated simulation files are created.
Table 419.  Group: Example Designs / Target Development Kit
Display Name Identifier Description
Select board EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT Specifies that when you select a development kit with a memory module, the generated example design contains all settings and fixed pin assignments to run on the selected board. You must select a development kit preset to generate a working example design for the specified development kit. Any IP settings not applied directly from a development kit preset will not have guaranteed results when testing the development kit. To exclude hardware support of the example design, select 'none' from the 'Select board' pull down menu. When you apply a development kit preset, all IP parameters are automatically set appropriately to match the selected preset. If you want to save your current settings, you should do so before you apply the preset. You can save your settings under a different name using File->Save as.

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