External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.5.4.6. Stratix 10 EMIF IP DDR3 Parameters: Board

Table 373.  Group: Board / Intersymbol Interference/Crosstalk
Display Name Identifier Description
Address and command ISI/crosstalk BOARD_DDR3_USER_AC_ISI_NS The address and command window reduction due to ISI and crosstalk effects. The number to be entered is the total loss of margin on both the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information.
Read DQS/DQS# ISI/crosstalk BOARD_DDR3_USER_RCLK_ISI_NS The reduction of the read data window due to ISI and crosstalk effects on the DQS/DQS# signal when driven by the memory device during a read. The number to be entered is the total loss of margin on the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information.
Read DQ ISI/crosstalk BOARD_DDR3_USER_RDATA_ISI_NS The reduction of the read data window due to ISI and crosstalk effects on the DQ signal when driven by the memory device during a read. The number to be entered is the total loss of margin on the setup and hold side (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information.
Write DQS/DQS# ISI/crosstalk BOARD_DDR3_USER_WCLK_ISI_NS The reduction of the write data window due to ISI and crosstalk effects on the DQS/DQS# signal when driven by the FPGA during a write. The number to be entered is the total loss of margin on the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information.
Write DQ ISI/crosstalk BOARD_DDR3_USER_WDATA_ISI_NS The reduction of the write data window due to ISI and crosstalk effects on the DQ signal when driven by the FPGA during a write. The number to be entered is the total loss of margin on the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information.
Use default ISI/crosstalk values BOARD_DDR3_USE_DEFAULT_ISI_VALUES You can enable this option to use default intersymbol interference and crosstalk values for your topology. Note that the default values are not optimized for your board. For optimal signal integrity, it is recommended that you do not enable this parameter, but instead perform I/O simulation using IBIS models and Hyperlynx*, and manually enter values based on your simulation results, instead of using the default values.
Table 374.  Group: Board / Board and Package Skews
Display Name Identifier Description
Average delay difference between address/command and CK BOARD_DDR3_AC_TO_CK_SKEW_NS The average delay difference between the address/command signals and the CK signal, calculated by averaging the longest and smallest address/command signal trace delay minus the maximum CK trace delay. Positive values represent address and command signals that are longer than CK signals and negative values represent address and command signals that are shorter than CK signals.
Maximum board skew within DQS group BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS The largest skew between all DQ and DM pins in a DQS group. This value affects the read capture and write margins.
Average delay difference between DQS and CK BOARD_DDR3_DQS_TO_CK_SKEW_NS The average delay difference between the DQS signals and the CK signal, calculated by averaging the longest and smallest DQS trace delay minus the CK trace delay. Positive values represent DQS signals that are longer than CK signals and negative values represent DQS signals that are shorter than CK signals.
Package deskewed with board layout (address/command bus) BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED Enable this parameter if you are compensating for package skew on the address, command, control, and memory clock buses in the board layout. Include package skew in calculating the following board skew parameters.
Package deskewed with board layout (DQS group) BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED Enable this parameter if you are compensating for package skew on the DQ, DQS, and DM buses in the board layout. Include package skew in calculating the following board skew parameters.
Maximum CK delay to DIMM/device BOARD_DDR3_MAX_CK_DELAY_NS The delay of the longest CK trace from the FPGA to any DIMM/device.
Maximum DQS delay to DIMM/device BOARD_DDR3_MAX_DQS_DELAY_NS The delay of the longest DQS trace from the FPGA to any DIMM/device
Maximum system skew within address/command bus BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS Maximum system skew within address/command bus refers to the largest skew between the address and command signals.
Maximum delay difference between DIMMs/devices BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS The largest propagation delay on DQ signals between ranks (applicable only when there is more than one rank). For example: when you configure two ranks using one DIMM there is a short distance between the ranks for the same DQ pin; when you implement two ranks using two DIMMs the distance is larger.
Maximum skew between DQS groups BOARD_DDR3_SKEW_BETWEEN_DQS_NS The largest skew between DQS signals.

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