External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

10.5.1. Signals to Monitor with the Signal Tap II Logic Analyzer

This topic lists the memory controller signals you should consider analyzing for different memory interfaces. This list is not exhaustive, but is a starting point.

For a description of each signal, refer to Volume 3: Reference Material of the External Memory Interface Handbook.

Monitor the following signals for UniPHY designs:

  • avl_addr
  • avl_rdata
  • avl_rdata_valid
  • avl_read_req
  • avl_ready
  • avl_wdata
  • avl_write_req
  • fail
  • pass
  • afi_cal_fail
  • afi_cal_success
  • test_complete
  • be_reg (QDRII only)
  • pnf_per_bit
  • rdata_reg
  • rdata_valid_reg
  • data_out
  • data_in
  • written_data_fifo|data_out
  • usequencer|state *
  • usequencer|phy_seq_rdata_valid
  • usequencer|phy_seq_read_fifo_q
  • usequencer|phy_read_increment_vfifo *
  • usequencer|phy_read_latency_counter
  • uread_datapath|afi_rdata_en
  • uread_datapath|afi_rdata_valid
  • uread_datapath|ddio_phy_dq
  • qvld_wr_address *
  • qvld_rd_address *

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