External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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7.5.1. Qsys Interfaces

The interfaces in the Stratix 10 External Memory Interface IP each have signals that can be connected in Qsys. The following tables list the signals available for each interface and provide a description and guidance on how to connect those interfaces.

Stratix 10 External Memory Interface IP Interfaces

Table 291.  Interface: afi_clk_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
afi_clk Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3, QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) clock output signal. The clock frequency in relation to the memory clock frequency depends on the Clock rate of user logic value set in the parameter editor.

Connect this interface to the (clock input) conduit of the custom AFI-based memory controller connected to the afi_conduit_end or any user logic block that requires the generated clock frequency.

Table 292.  Interface: afi_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
afi_cal_success Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3, QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) signals between the external memory interface IP and the custom AFI-based memory controller.

Connect this interface to the AFI conduit of the custom AFI-based memory controller.

afi_cal_fail Output
afi_cal_req Input
afi_rlat Output
afi_wlat Output
afi_addr Input
afi_rst_n Input
afi_wdata_valid Input
afi_wdata Input
afi_rdata_en_full Input
afi_rdata Output
afi_rdata_valid Output
afi_rrank Input
afi_wrank Input
afi_ba Input
  • DDR3, DDR4, RLDRAM 3
  • Hard PHY only
afi_cs_n Input
  • DDR3, DDR4, LPDDR3, RLDRAM 3
  • Hard PHY only
afi_cke Input
  • DDR3, DDR4, LPDDR3
  • Hard PHY only
afi_odt Input
afi_dqs_burst Input
afi_ap Input
  • QDR IV
  • Hard PHY only
 
afi_pe_n Output
afi_ainv Input
afi_ld_n Input
afi_rw_n Input
afi_cfg_n Input
afi_lbk0_n Input
afi_lbk1_n Input
afi_rdata_dinv Output
  • QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) signals between the external memory interface IP and the custom AFI-based memory controller.

Connect this interface to the AFI conduit of the custom AFI-based memory controller.

afi_wdata_dinv Input
afi_we_n Input
  • DDR3, RLDRAM 3
  • Hard PHY only
The Altera PHY Interface (AFI) signals between the external memory interface IP and the custom AFI-based memory controller.

Connect this interface to the AFI conduit of the custom AFI-based memory controller.

For more information, refer to the AFI 4.0 Specification.

afi_dm Input
  • DDR3, LPDDR3, RLDRAM 3
  • Hard PHY only
  • Enable DM pins=True
afi_ras_n Input
  • DDR3
  • Hard PHY only
afi_cas_n Input
afi_rm Input
  • DDR3
  • Hard PHY only
  • LRDIMM with Number of rank multiplication pins > 0
afi_par Input
  • DDR3
  • Hard PHY only
  • RDIMM/LRDIMM
  • DDR4
  • Hard PHY only
  • Enable alert_n/par pins = True
afi_bg Input
  • DDR4
  • Hard PHY only
afi_act_n Input
afi_dm_n Input
  • DDR4
  • Hard PHY only
  • Enable DM pins=True
afi_ref_n Input
  • RLDRAM 3
  • Hard PHY only
Table 293.  Interface: afi_half_clk_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
afi_half_clk Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3, QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) half clock output signal. The clock runs at half the frequency of the AFI clock (afi_clk clock).

Connect this interface to the clock input conduit of the user logic block that needs to be clocked at the generated clock frequency.

Table 294.  Interface: afi_reset_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
afi_reset_n Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3, QDR IV
  • Hard PHY only
The Altera PHY Interface (AFI) reset output signal. Asserted when the PLL becomes unlocked or when the PHY is reset. Asynchronous assertion and synchronous deassertion.

Connect this interface to the reset input conduit of the custom AFI-based memory controller connected to the afi_conduit_end and all the user logic blocks that are under the AFI clock domain afi_clk or afi_half_clk clock).

Table 295.  Interface: cal_debug_avalon_slaveInterface type: Avalon Memory-Mapped Slave
Signals in Interface Direction Availability Description
cal_debug_waitrequest Output
  • EMIF Debug Toolkit
  • On-Chip Debug Port=Export
The Avalon-MM signals between the external memory interface IP and the external memory interface Debug Component.

Connect this interface to the (to_ioaux) Avalon-MM master of the Stratix® 10 EMIF Debug Component IP or to (cal_debug_out_avalon_master) Avalon-MM master of the other external memory interface IP that has exported the interface. If you are not using the Altera EMIF Debug Toolkit, connect this interface to the Avalon-MM master of the custom debug logic.

When in daisy-chaining mode, ensure one of the connected Avalon masters is either the Stratix® 10 EMIF Debug Component IP or the external memory interface IP with EMIF Debug Toolkit/On-Chip Debug Port set to Add EMIF Debug Interface.

cal_debug_read Input
cal_debug_write Input
cal_debug_addr Input
cal_debug_read_data Output
cal_debug_write_data Input
cal_debug_byteenable Input
cal_debug_read_data_valid Output
Table 296.  Interface: cal_debug_clk_clock_sinkInterface type: Clock Input
Signals in Interface Direction Availability Description
cal_debug_clk Input
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
The calibration debug clock input signal.

Connect this interface to the (avl_clk_out) clock output of the Stratix® 10 EMIF Debug Component IP or to (cal_debug_out_clk_clock_source) clock input of the other external memory interface IP, depending on which IP the cal_debug_avalon_slave interface is connecting to. If you are not using the Altera EMIF Debug Toolkit, connect this interface to the clock output of the custom debug logic.

Table 297.  Interface: cal_debug_out_avalon_masterInterface type: Avalon Memory-Mapped Master
Signals in Interface Direction Availability Description
cal_debug_out_waitrequest Input
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
  • Add EMIF Debug Interface with Enable Daisy-Chaining for EMIF Debug Toolkit/ On-Chip Debug Port=True
The Avalon-MM signals between the external memory interface IP and the other external memory interface IP.

Connect this interface to the (cal_debug_avalon_slave) Avalon-MM Master of the external memory interface IP that has exported the interface .

cal_debug_out_read Output
cal_debug_out_write Output
cal_debug_out_addr Output
cal_debug_out_read_data Input
cal_debug_out_write_data Output
cal_debug_out_byteenable Output
cal_debug_out_read_data_valid Input
Table 298.  Interface: cal_debug_out_clk_clock_sourceInterface type: Clock Output
Signals in Interface Direction Availability Description
cal_debug_out_clk Output
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
  • Add EMIF Debug Interface with Enable Daisy-Chaining for EMIF Debug Toolkit/ On-Chip Debug Port=True
The calibration debug clock output signal.

For EMIF Debug Toolkit/On-Chip Debug Port=Export with Enable Daisy-Chaining for EMIF Debug Toolkit/ On-Chip Debug Port=True, the clock frequency follows the cal_debug_clk frequency. Otherwise, the clock frequency in relation to the memory clock frequency depends on the Clock rate of user logic value set in the parameter editor.

Connect this interface to the (cal_debug_out_reset_reset_source) clock input of the other external memory interface IP where the cal_debug_avalon_master interface is being connected to or to any user logic block that needs to be clocked at the generated clock frequency.

Table 299.  Interface: cal_debug_out_reset_reset_sourceInterface type: Reset Output
Signals in Interface Direction Availability Description
cal_debug_out_reset_n Output
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
  • Add EMIF Debug Interface with Enable Daisy-Chaining for EMIF Debug Toolkit/ On-Chip Debug Port=True
The calibration debug reset output signal. Asynchronous assertion and synchronous deassertion.

Connect this interface to the (cal_debug_reset_reset_sink) reset input of the other external memory interface IP where the cal_debug_avalon_master interface being connected to and all the user logic blocks that are under the calibration debug clock domain (cal_debug_out_clk clock reset). If you are not using the Altera EMIF Debug Toolkit, connect this interface to the reset output of the custom debug logic.

Table 300.  Interface: cal_debug_reset_reset_sinkInterface type: Reset Intput
Signals in Interface Direction Availability Description
cal_debug_reset_n Input
  • EMIF Debug Toolkit / On-Chip Debug Port=Export
The calibration debug reset input signal. Require asynchronous assertion and synchronous deassertion.

Connect this interface to the (avl_rst_out) reset output of the Stratix® 10 EMIF Debug Component IP or to (cal_debug_out_reset_reset_source) clock input of the other external memory interface IP, depending on which IP the cal_debug_avalon_slave interface is being connected to.

Table 301.  Interface: clks_sharing_master_out_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
clks_sharing_master_out Input
  • Core clocks sharing=Master
The core clock output signals.

Connect this interface to the (clks_sharing_slave_in_conduit_end) conduit of the other external memory interface IP with the Core clock sharing set to slave or other PLL Slave.

Table 302.  Interface: clks_sharing_slave_in_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
clks_sharing_slave_in Input
  • Core clocks sharing=Slave
The core clock input signals.

Connect this interface to the (clks_sharing_master_out_conduit_end) conduit of the other external memory interface IP with the Core clock sharing set to Master or other PLL Master.

Table 303.  Interface: ctrl_amm_avalon_slaveInterface type: Avalon Memory-Mapped Slave
Signals in Interface Direction Availability Description
amm_ready Output
  • DDR3, DDR4 with Hard PHY & Hard Controller
  • QDR II/II+/II+ Xtreme, QDR IV
The Avalon-MM signals between the external memory interface IP and the user logic.

Connect this interface to the Avalon-MM Master of the user logic that needs to access the external memory device. For QDR II/II+/II+ Xtreme, connect the ctrl_amm_avalon_slave_0 to the user logic for read request and connect the ctrl_amm_avalon_slave_1 to the user logic for write request.

In Ping Pong PHY mode, each interface controls only one memory device. Connect ctrl_amm_avalon_slave_0 to the user logic that will access the first memory device, and connect ctrl_amm_avalon_slave_1 to the user logic that will access the secondary memory device.

amm_read Input
amm_write Input
amm_address Input
amm_readdata Output
amm_writedata Input
amm_burstcount Input
amm_readdatavalid Output
amm_byteenable Input
  • DDR3, DDR4 with Hard PHY & Hard Controller and Enable DM pins=True
  • QDR II/II+/II+ Xtreme with Enable BWS# pins=True
Table 304.  Interface: ctrl_auto_precharge_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
ctrl_auto_precharge_req Input
  • DDR3, DDR4 with Hard PHY & Hard Controller and Enable Auto-Precharge Control=True
The auto-precharge control input signal. Asserting the ctrl_auto_precharge_req signal while issuing a read or write burst instructs the external memory interface IP to issue read or write with auto-precharge to the external memory device. This precharges the row immediately after the command currently accessing it finishes, potentially speeding up a future access to a different row of the same bank.

Connect this interface to the conduit of the user logic block that controls when the external memory interface IP needs to issue read or write with auto-precharge to the external memory device.

Table 305.  Interface: ctrl_ecc_user_interrupt_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
ctrl_ecc_user_interrupt Output
  • DDR3, DDR4 with Hard PHY & Hard Controller and Enable Error Detection and Correction Logic = True

Controller ECC user interrupt interface for connection to a custom control block that must be notified when ECC errors occur.

Table 306.  Interface: ctrl_mmr_avalon_slaveInterface type: Avalon Memory-Mapped Slave
Signals in Interface Direction Availability Description
mmr_waitrequest Output
  • DDR3, DDR4, LPDDR3 with Hard PHY & Hard Controller and Enable Memory-Mapped Configuration and Status Register (MMR)=True

The Avalon-MM signals between the external memory interface IP and the user logic.

Connect this interface to the Avalon-MM master of the user logic that needs to access the Memory-Mapped Configuration and Status Register (MMR) in the external memory interface IP.

mmr_read Input
mmr_write Input
mmr_address Input
mmr_readdata Output
mmr_writedata Input
mmr_burstcount Input
mmr_byteenable Input
mmr_beginbursttransfer Input
mmr_readdatavalid Output
Table 307.  Interface: ctrl_power_down_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
ctrl_power_down_ack Output
  • DDR3, DDR4, LPDDR3 with Hard PHY & Hard Controller and Enable Auto Power Down=True
The auto power-down acknowledgment signals. When the ctrl_power_down_ack signal is asserted, it indicates that the external memory interface IP is placing the external memory device into power-down mode.

Connect this interface to the conduit of the user logic block that requires the auto power-down status, or leave it unconnected.

Table 308.  Interface: ctrl_user_priority_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
ctrl_user_priority_hi Input
  • DDR3, DDR4, LPDDR3 with Hard PHY & Hard Controller
  • Avalon Memory-Mapped and Enable Command Priority Control=true
The command priority control input signal. Asserting the ctrl_user_priority_hi signal while issuing a read or write request instructs the external memory interface to treat it as a high-priority command. The external memory interface attempts to execute high-priority commands sooner, to reduce latency.

Connect this interface to the conduit of the user logic block that determines when the external memory interface IP treats the read or write request as a high-priority command.

Table 309.  Interface: emif_usr_clk_clock_sourceInterface type: Clock Output
Signals in Interface Direction Availability Description
emif_usr_clk Output
  • DDR3, DDR4, LPDDR3, with Hard PHY & Hard Controller
  • QDR II/II+/II+ Xtreme
  • QDR IV
The user clock output signal. The clock frequency in relation to the memory clock frequency depends on the Clock rate of user logic value set in the parameter editor.

Connect this interface to the clock input of the respective user logic connected to the ctrl_amm_avalon_slave_0 interface, or to any user logic block that must be clocked at the generated clock frequency.

Table 310.  Interface: emif_usr_reset_reset_sourceInterface type: Reset Output
Signals in Interface Direction Availability Description
emif_usr_reset_n Output
  • DDR3, DDR4, LPDDR3 with Hard PHY & Hard Controller
  • QDR II/II+/II+ Xtreme
  • QDR IV
The user reset output signal. Asserted when the PLL becomes unlocked or the PHY is reset. Asynchronous assertion and synchronous deassertion.

Connect this interface to the clock input of the respective user logic connected to the ctrl_amm_avalon_slave_0 interface, or to any user logic block that must be clocked at the generated clock frequency.

Table 311.  Interface: emif_usr_clk_sec_clock_sourceInterface type: Clock Output
Signals in Interface Direction Availability Description
emif_usr_clk_sec Output
  • DDR3, DDR4, with Ping Pong PHY
The user clock output signal. The clock frequency in relation to the memory clock frequency depends on the Clock rate of user logic value set in the parameter editor.

Connect this interface to the clock input of the respective user logic connected to the ctrl_amm_avalon_slave_1 interface, or to any user logic block that must be clocked at the generated clock frequency.

Table 312.  Interface: emif_usr_reset_sec_reset_sourceInterface type: Reset Output
Signals in Interface Direction Availability Description
emif_usr_reset_n_sec Output
  • DDR3, DDR4, with Ping Pong PHY
The user reset output signal. Asserted when the PLL becomes unlocked or the PHY is reset. Asynchronous assertion and synchronous deassertion.

Connect this interface to the clock input of the respective user logic connected to the ctrl_amm_avalon_slave_1 interface, or to any user logic block that must be clocked at the generated clock frequency.

Table 313.  Interface: global_reset_reset_sinkInterface type: Reset Input
Signals in Interface Direction Availability Description
global_reset_n Input
  • Core Clock Sharing=No Sharing / Master
The global reset input signal. Asserting the global_reset_n signal causes the external memory interface IP to be reset and recalibrated.

Connect this interface to the reset output of the asynchronous or synchronous reset source that controls when the external memory interface IP needs to be reset and recalibrated.

Table 314.  Interface: mem_conduit_endInterface type: Conduit

The memory interface signals between the external memory interface IP and the external memory device.

Export this interface to the top level for I/O assignments. Typically mem_rm[0] and mem_rm[1] connect to CS2# and CS3# of the memory buffer of all LRDIMM slots.

Signals in Interface Direction Availability
mem_ck Output Always available
mem_ck_n Output
mem_reset_n Output
mem_a Output
mem_k_n Output
  • QDR II
mem_ras_n Output
  • DDR3
mem_cas_n Output
mem_odt Output
  • DDR3, DDR4, LPDDR3
mem_dqs Bidirectional
mem_dqs_n Bidirectional
mem_ba Output
  • DDR3, DDR4, RLDRAM 3
mem_cs_n Output
  • DDR3, DDR4, LPDDR3, RLDRAM 3
mem_dq Bidirectional
mem_we_n Output
  • DDR3, RLDRAM 3
mem_dm Output
  • DDR3, LPDDR3, RLDRAM 3 with Enable DM pins=True
mem_rm Output
  • DDR3, RLDRAM 3 with Memory format=LRDIMM and Number of rank multiplication pins > 0
mem_par Output
  • DDR3 with Memory format=RDIMM / LRDIMM
  • DDR4 with Enable alert_n/par pins=True
mem_alert_n Input
mem_cke Output
  • DDR3, DDR4, LPDDR3
mem_bg Output
  • DDR4
mem_act_n Output
mem_dbi_n Bidirectional
  • DDR4 with Enable DM pins=True or Write DBI=True or Read DBI=True
mem_k Output
  • QDR II/II+/II+ Xtreme
mem_wps_n Output
mem_rps_n Output
mem_doff_n Output
mem_d Output
mem_q Input
mem_cq Input
mem_cq_n Input
mem_bws_n Output
mem_dk Output
mem_dk_n Output
mem_ref_n Output
mem_qk Input
  • QDR II/II+/II+ Xtreme with Enable BWS# pins=True
mem_qk_n Input
  • RLDRAM 3
mem_ap Output
  • QDR IV with Use Address Parity Bit=True
mem_pe_n Input
  • QDR IV with Use Address Parity Bit=True
mem_ainv Output
  • QDR IV with Address Bus Inversion=True
mem_lda_n Output
  • QDR IV
mem_lda_b Output
  • QDR IV
mem_rwa_n Output
  • QDR IV
mem_rwb_n Output
  • QDR IV
mem_cfg_n Output
  • QDR IV
mem_lbk0_n Output
  • QDR IV
mem_lbk1_n Output
  • QDR IV
mem_dka Output
  • QDR IV
mem_dka_n Output
  • QDR IV
mem_dkb Output
  • QDR IV
mem_dkb_n Output
  • QDR IV
mem_qka Input
  • QDR IV
mem_qka_n Input
  • QDR IV
mem_qkb Input
  • QDR IV
mem_qkb_n Input
  • QDR IV
mem_dqa Bidirectional
  • QDR IV
mem_dqb Bidirectional
  • QDR IV
mem_dinva Bidirectional
  • QDR IV with Data Bus Inversion=True
mem_dinvb Bidirectional
  • QDR IV with Data Bus Inversion=True
Table 315.  Interface: oct_conduit_endInterface type: Conduit
Signals in Interface Direction Availability Description
oct_rzqin Input Always available The On-Chip Termination (OCT) RZQ reference resistor input signal.

Export this interface to the top level for I/O assignments.

Table 316.  Interface: pll_ref_clk_clock_sink
Signals in Interface Interface Type Direction Availability Description
pll_ref_clk Clock Input Input
  • Core clock sharing=No Sharing / Master
The PLL reference clock input signal.

Connect this interface to the clock output of the clock source that matches the PLL reference clock frequency value set in the parameter editor.

Table 317.  Interface: status_conduit_end
Signals in Interface Interface Type Direction Availability Description
local_cal_success Conduit Output Always available The PHY calibration status output signals. When the local_cal_success signal is asserted, it indicates that the PHY calibration was successful. Otherwise, if local_cal_fail signal is asserted, it indicates that PHY calibration has failed.

Connect this interface to the conduit of the user logic block that requires the calibration status information, or leave it unconnected.

local_cal_fail

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