1.1.11. QDR IV SRAM Commands and Addresses, AP, and AINV Signals
QDR IV SRAM devices have the ability to invert all address pins to reduce potential simultaneous switching noise. Such inversion is accomplished using the Address Inversion Pin for Address and Address Parity Inputs (AINV), which assumes an address parity of 0, and indicates whether the address bus and address parity are inverted.
The above features are available as Option Control under Configuration Register Settings in Arria 10 EMIF IP. The commands and addresses must meet the memory address and command setup (tAS, tCS) and hold (tAH, tCH) time requirements.
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