External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.15.1. Performing Early I/O Timing Analysis for Stratix 10 EMIF IP

To perform early I/O timing analysis, follow these steps:
  1. Instantiate a Stratix 10 EMIF IP core.
    1. On the Memory Timing tab, enter accurate memory parameters.
    2. On the Board Timing tab, enter accurate values for Slew Rate, Intersymbol Interference, and Board and Package Skews.
  2. After generating your IP core, create a Quartus Prime project and select your device from the Available devices list.
  3. To launch the TimeQuest Timing Analyzer, select TimeQuest Timing Analyzer from the Tools menu.
  4. To run early I/O timing analysis:
    1. Select Run Tcl Script from the Script menu.
    2. Run submodule\< variation_name >_report_io_timing.tcl.

The following figure shows an early I/O timing analysis from the TimeQuest Timing Analyzer using a DDR3 example design.

Figure 99.  Report DDR Timing Results


Report DDR details the read capture, write, address and command, DQS gating, and write leveling timing analyses, which are identical to those obtained after a full design compilation. Core FPGA timing paths are not included in early I/O timing analysis.

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