External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.4.2. Generated Files for Arria® 10 External Memory Interface IP

When you complete the IP generation flow, there are generated files created in your project directory. The directory structure created varies somewhat, depending on the tool used to parameterize and generate the IP.
Note: The PLL parameters are statically defined in the <variation_name>_parameters.tcl at generation time. To ensure timing constraints and timing reports are correct, when you edit the PLL parameters, apply those changes to the PLL parameters in this file.

The following table lists the generated directory structure and key files created when generating the IP.

Table 113.  Generated Directory Structure and Key Files for Synthesis

Directory

File Name

Description

working_dir/ working_dir/<Top-level Name>/ The Qsys files for your IP component or system based on your configuration.
working_dir/<Top-level Name>/ *.ppf Pin Planner File for use with the Pin Planner.
working_dir/<Top-level Name>/synth/ <Top-level Name>.v or <Top-level Name>.vhd Qsys generated top-level wrapper for synthesis.
working_dir/<Top-level Name>/altera_emif_<acds version>/synth/ *.v or (*.v and *.vhd) Arria 10 EMIF (non-HPS) top-level dynamic wrapper files for synthesis. This wrapper instantiates the EMIF ECC and EMIF Debug Interface IP core.
working_dir/<Top-level Name>/altera_emif_a10_hps_<acds version>/synth/ *.v or (*.v and *.vhd) Arria 10 EMIF for HPS top-level dynamic wrapper files for synthesis.
working_dir/<Top-level Name>/altera_emif_a10_hps_<acds version>/synth/ *.sv, *.sdc, *.tcl and *.hex and *_readme.txt Arria 10 EMIF Core RTL, constraints files, ROM content files and information files for synthesis.

Whether the file type is set to Verilog or VHDL, all the Arria 10 EMIF Core RTL files will be generated as a SystemVerilog file. The readme.txt file contains information and guidelines specific to your configuration.

working_dir/<Top-level Name>/<other components>_<acds version>/synth/ * Other EMIF ECC, EMIF Debug Interface IP or Merlin Interconnect component files for synthesis.
Table 114.  Generated Directory Structure and Key Files for Simulation

Directory

File Name

Description

working_dir/<Top-level Name>/sim/ <Top-level Name>.v or <Top-level Name>.vhd Qsys generated top-level wrapper for simulation.
working_dir/<Top-level Name>/sim/<simulator vendor>/ *.tcl, *cds.lib, *.lib, *.var, *.sh, *.setup Simulator-specific simulation scripts.
working_dir/<Top-level Name>/altera_emif_<acds version>/sim/ *.v or *.vhd Arria 10 EMIF (non-HPS) top-level dynamic wrapper files for simulation. This wrapper instantiates the EMIF ECC and EMIF Debug Interface IP cores.
working_dir/<Top-level Name>/altera_emif_a10_hps_<acds version>/sim/ *.v or *.vhd Arria 10 EMIF for HPS top-level dynamic wrapper files for simulation.
working_dir/<Top-level Name>/altera_emif_arch_nf_<acds version>/sim/ *sv or (*.sv and *.vhd), *.hex and *_readme.txt Arria 10 EMIF RTL, ROM content files, and information files for simulation.

For SystemVerilog / Mix language simulator, you may directly use the files from this folder. For VHDL-only simulator, other than the ROM content files, you have to use files in <current folder>/mentor directory instead.

The readme.txt file contains information and guidelines specific to your configuration.

     
working_dir/<Top-level Name>/<other components>_<acds version>/sim/   Other EMIF ECC, EMIF Debug Interface IP, or Merlin Interconnect component files for simulation
     
Table 115.  Generated Directory Structure and Key Files for Qsys-Generated Testbench System

Directory

File Name

Description

working_dir/<Top-level Name>_tb/ *.qsys The Qsys files for the QSYS generated testbench system.
working_dir/<Top-level Name>_tb/sim/ <Top-level Name>.v or <Top-level Name>.vhd Qsys generated testbench file for simulation.

This wrapper instantiates BFM components. For Arria 10 EMIF IP, this module should instantiate the memory model for the memory conduit being exported from your created system.

working_dir/<Top-level Name>_tb/<Top-level Name>_<id>/sim/ <Top-level Name>.v or <Top-level Name>.vhd Qsys generated top-level wrapper for simulation.
working_dir/<Top-level Name>_tb/sim/<simulator vendor>/ *.tcl, *cds.lib, *.lib, *.var, *.sh, *.setup Simulator-specific simulation scripts.
working_dir/<Top-level Name>_tb/sim/<simulator vendor>/ *.v or *.vhd Arria 10 EMIF (non-HPS) top-level dynamic wrapper files for simulation.

This wrapper instantiates the EMIF ECC and EMIF Debug Interface IP cores.

working_dir/<Top-level Name>_tb/altera_emif_a10_hps_<acds version>/sim/ *.v or *.vhd Arria 10 EMIF for HPS top-level dynamic wrapper files for simulation.
working_dir/<Top-level Name>_tb/altera_emif_arch_nf_<acds version>/sim/ *sv or (*.sv and *.vhd), *.hex and *_readme.txt Arria 10 EMIF Core RTL, ROM content files and information files for simulation.

For SystemVerilog / Mix language simulator, you may use the files from this folder. For VHDL-only simulator, other than the ROM content files, you must use files in the <current folder>/mentor directory instead. The readme.txt file contains information and guidelines specific to your configuration.

working_dir/<Top-level Name>_tb/sim/altera_emif_arch_nf_<acds version>/sim/mentor/ *.sv and *.vhd Arria 10 EMIF Core RTL for simulation.

Only available when you create a VHDL simulation model. All .sv files are Mentor-tagged encrypted IP (IEEE Encrypted Verilog) for VHDL-only simulator support.

working_dir/<Top-level Name>_tb/<other components>_<acds version>/sim/ * Other EMIF ECC, EMIF Debug Interface IP or Merlin Interconnect component files for simulation.
working_dir/<Top-level Name>_tb/<other components>_<acds version>/sim/mentor/ * Other EMIF ECC, EMIF Debug Interface IP or Merlin Interconnect component files for simulation.

Only available depending on individual component simulation model support and when creating a VHDL simulation model. All files in this folder are Mentor-tagged encrypted IP (IEEE Encrypted Verilog) for VHDL-only simulator support.

Table 116.  Generated Directory Structure and Key Files for Example Simulation Designs

Directory

File Name

Description

working_dir/*_example_design*/ *.qsys, *.tcl and readme.txt Qsys files, generation scripts, and information for generating the Arria 10 EMIF IP example design.

These files are available only when you generate an example design. You may open the .qsys file in Qsys to add more components to the example design.

working_dir/*_example_design*/sim/ed_sim/sim/ *.tcl, *cds.lib, *.lib, *.var, *.sh, *.setup Simulator-specific simulation scripts.
working_dir/*_example_design*/sim/ed_sim/<simulator vendor>/ *.v or *.vhd Qsys-generated top-level wrapper for simulation.
working_dir/*_example_design*/sim/ip/ed_sim/ed_sim_emif_0/altera_emif_<acds_version>/simip/ed_sim/ed_sim_emif_0/altera_emif_ *.v or *.vhd) Arria 10 EMIF (non-HPS) top-level dynamic wrapper files for simulation. This wrapper instantiates the EMIF ECC and EMIF Debug Interface IP cores.
working_dir/*_example_design*/sim/ip/ed_sim/ed_sim_emif_0/altera_emif_arch_nf_<acds_version>/sim/ *sv or (*.sv and *.vhd), *.hex and *_readme.txt Arria 10 EMIF RTL, ROM content files, and information files for simulation. For SystemVerilog / Mix language simulator, you may directly use the files from this folder. For VHDL-only simulator, other than the ROM content files, you have to use files in <current folder>/mentor directory instead. The readme.txt file contains information and guidelines specific to your configuration.
working_dir/*_example_design*/sim/ed_sim/<other components>_<acds_version>/sim/

and

working_dir/*_example_design*/sim/ip/ed_sim/<other components>/sim/

and

working_dir/*_example_design*/sim/ip/ed_sim/<other components>/<other components>_<acds_version>
* Other EMIF ECC, EMIF Debug Interface IP, or Merlin Interconnect component files for simulation
Table 117.  Generated Directory Structure and Key Files for Example Synthesis Designs

Directory

File Name

Description

working_dir/*_example_design*/ *.qsys, *.tcl and readme.txt Qsys files, generation scripts, and information for generating the Arria 10 EMIF IP example design.

These files are available only when you generate an example design. You may open the .qsys file in Qsys to add more components to the example design.

working_dir/*_example_design*/qii/ed_synth/synth *.v or (*.v and *.vhd) Qsys-generated top-level wrapper for synthesis.
working_dir/*_example_design*/qii/ip/ed_synth/ed_synth_emif_0/altera_emif_<acds_version>/synth *.v or (*.v and *.vhd) Arria 10 EMIF (non HPS) top-level dynamic wrapper files for synthesis. This wrapper instantiates the EMIF ECC and EMIF debug interface core IP.
working_dir/*_example_design*/qii/ip/ed_synth/ed_synth_emif_0/altera_emif_arch_nf_<acds_version>/synth/ *.sv, *.sdc, *.tcl, *.hex, and *_readme.txt

Arria 10 EMIF Core RTL, constraints files, ROM content files and information files for synthesis.

Whether the file type is set to Verilog or VHDL, all the Arria 10 EMIF Core RTL files are generated as a SystemVerilog file. The readme.txt file contains information and guidelines specific to your configuration.

working_dir/*_example_design*/sim/ed_synth/<other components>_<acds_version>/synth

and

working_dir/*_example_design*/sim/ip/ed_synth/<other_components>/synth/

and

working_dir/*_example_design*/sim/ip/ed_synth/<other_components>/<other_components>_<acds_version>/synth
* Other EMIF ECC, EMIF debug interface IP, or Merlin interconnect component files for synthesis.

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