External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.14. Early I/O Timing Estimation for Arria 10 EMIF IP

Early I/O timing analysis allows you to run I/O timing analysis without first compiling your design. You can use early I/O timing analysis to quickly evaluate whether adequate timing margin exists on the I/O interface between the FPGA and external memory device.

Early I/O timing analysis performs the following analyses:

  • Read analysis
  • Write analysis
  • Address and command analysis
  • DQS gating analysis
  • Write leveling analysis

Early I/O timing analysis takes into consideration the following factors:

  • The timing parameters of the memory device
  • The speed and topology of the memory interface
  • The board timing and ISI characteristics
  • The timing of the selected FPGA device

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