External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

11.2.7.1. Back-to-Back User-Controlled Refresh Usage in Arria® 10

The following diagram illustrates the back-to-back refresh model for optimized hard memory controller (HMC) performance in Arria® 10 devices.

For optimal performance, ensure that you deassert the Refresh request after receiving the acknowledgement pulse. You can implement a timer to track tRFC before asserting the next Refresh request. Failure to deassert the Refresh request can delay memory access to the rank not in refresh.

Did you find the information on this page useful?

Characters remaining:

Feedback Message