External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.4.8.5. Arria 10 EMIF IP RLDRAM 3 Parameters: Board

Table 275.  Group: Board / Intersymbol Interference/Crosstalk
Display Name Identifier Description
Address and command ISI/crosstalk BOARD_RLD3_USER_AC_ISI_NS The address and command window reduction due to ISI and crosstalk effects. The number to be entered is the total loss of margin on both the setup and hold sides (measured loss on the setup side + measured loss on the hold side). Refer to the EMIF Simulation Guidance wiki page for additional information.
QK/QK# ISI/crosstalk BOARD_RLD3_USER_RCLK_ISI_NS QK/QK# ISI/crosstalk describes the reduction of the read data window due to intersymbol interference and crosstalk effects on the QK/QK# signal when driven by the memory device during a read. The number to be entered in the Quartus Prime software is the total of the measured loss of margin on the setup side plus the measured loss of margin on the hold side. Refer to the EMIF Simulation Guidance wiki page for additional information.
DK/DK# ISI/crosstalk BOARD_RLD3_USER_WCLK_ISI_NS DK/DK# ISI/crosstalk describes the reduction of the write data window due to intersymbol interference and crosstalk effects on the DK/DK# signal when driven by the FPGA during a write. The number to be entered in the Quartus Prime software is the total of the measured loss of margin on the setup side plus the measured loss of margin on the hold side. Refer to the EMIF Simulation Guidance wiki page for additional information.
Write DQ ISI/crosstalk BOARD_RLD3_USER_WDATA_ISI_NS The reduction of the write data window due to ISI and crosstalk effects on the DQ signal when driven by the FPGA during a write. The number to be entered is the total of the measured loss of margin on the setup side plus the measured loss of margin on the hold side. Refer to the EMIF Simulation Guidance wiki page for additional information.
Use default ISI/crosstalk values BOARD_RLD3_USE_DEFAULT_ISI_VALUES You can enable this option to use default intersymbol interference and crosstalk values for your topology. Note that the default values are not optimized for your board. For optimal signal integrity, it is recommended that you do not enable this parameter, but instead perform I/O simulation using IBIS models and Hyperlynx*, and manually enter values based on your simulation results, instead of using the default values.
Table 276.  Group: Board / Board and Package Skews
Display Name Identifier Description
Average delay difference between address/command and CK BOARD_RLD3_AC_TO_CK_SKEW_NS The average delay difference between the address/command signals and the CK signal, calculated by averaging the longest and smallest address/command signal trace delay minus the maximum CK trace delay. Positive values represent address and command signals that are longer than CK signals and negative values represent address and command signals that are shorter than CK signals.
Maximum board skew within QK group BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS Maximum board skew within QK group refers to the largest skew between all DQ and DM pins in a QK group. This value can affect the read capture and write margins.
Average delay difference between DK and CK BOARD_RLD3_DK_TO_CK_SKEW_NS This parameter describes the average delay difference between the DK signals and the CK signal, calculated by averaging the longest and smallest DK trace delay minus the CK trace delay. Positive values represent DK signals that are longer than CK signals and negative values represent DK signals that are shorter than CK signals.
Package deskewed with board layout (address/command bus) BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED Enable this parameter if you are compensating for package skew on the address, command, control, and memory clock buses in the board layout. Include package skew in calculating the following board skew parameters.
Package deskewed with board layout (QK group) BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED If you are compensating for package skew on the QK bus in the board layout (hence checking the box here), please include package skew in calculating the following board skew parameters.
Maximum CK delay to device BOARD_RLD3_MAX_CK_DELAY_NS The maximum CK delay to device refers to the delay of the longest CK trace from the FPGA to any device.
Maximum DK delay to device BOARD_RLD3_MAX_DK_DELAY_NS The maximum DK delay to device refers to the delay of the longest DK trace from the FPGA to any device.
Maximum system skew within address/command bus BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS Maximum system skew within address/command bus refers to the largest skew between the address and command signals.
Maximum delay difference between devices BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS This parameter describes the largest propagation delay on the DQ signals between ranks. For example, in a two-rank configuration where devices are placed in series, there is an extra propagation delay for DQ signals going to and coming back from the furthest device compared to the nearest device. This parameter is only applicable when there is more than one rank.
Maximum skew between DK groups BOARD_RLD3_SKEW_BETWEEN_DK_NS This parameter describes the largest skew between DK signals in different DK groups.

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