7.4.7.1. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: General

External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

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Date 3/06/2023

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7.4.7.1. Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: General

Table 239. Group: General / FPGA
Display Name	Identifier	Description
Speed grade	PHY_FPGA_SPEEDGRADE_GUI	Indicates the device speed grade, and whether it is an engineering sample (ES) or production device. This value is based on the device that you select in the parameter editor. If you do not specify a device, the system assumes a default value. Ensure that you always specify the correct device during IP generation, otherwise your IP may not work in hardware.

Table 240. Group: General / Interface
Display Name	Identifier	Description
Configuration	PHY_CONFIG_ENUM	Specifies the configuration of the memory interface. The available options depend on the protocol in use. Options include Hard PHY and Hard Controller, Hard PHY and Soft Controller, or Hard PHY only. If you select Hard PHY only, the AFI interface is exported to allow connection of a custom memory controller or third-party IP.
Instantiate two controllers sharing a Ping Pong PHY	PHY_PING_PONG_EN	Specifies the instantiation of two identical memory controllers that share an address/command bus through the use of Ping Pong PHY. This parameter is available only if you specify the Hard PHY and Hard Controller option. When this parameter is enabled, the IP exposes two independent Avalon interfaces to the user logic, and a single external memory interface with double width for the data bus and the CS#, CKE, ODT, and CK/CK# signals.

Table 241. Group: General / Clocks
Display Name	Identifier	Description
Core clocks sharing	PHY_CORE_CLKS_SHARING_ENUM	When a design contains multiple interfaces of the same protocol, rate, frequency, and PLL reference clock source, they can share a common set of core clock domains. By sharing core clock domains, they reduce clock network usage and avoid clock synchronization logic between the interfaces. To share core clocks, denote one of the interfaces as "Master", and the remaining interfaces as "Slave". In the RTL, connect the clks_sharing_master_out signal from the master interface to the clks_sharing_slave_in signal of all the slave interfaces. Both master and slave interfaces still expose their own output clock ports in the RTL (for example, emif_usr_clk, afi_clk), but the physical signals are equivalent, hence it does not matter whether a clock port from a master or a slave is used. As the combined width of all interfaces sharing the same core clock increases, you may encounter timing closure difficulty for transfers between the FPGA core and the periphery.
Memory clock frequency	PHY_MEM_CLK_FREQ_MHZ	Specifies the operating frequency of the memory interface in MHz. If you change the memory frequency, you should update the memory latency parameters on the "Memory" tab and the memory timing parameters on the "Mem Timing" tab.
Use recommended PLL reference clock frequency	PHY_QDR2_DEFAULT_REF_CLK_FREQ	Specifies that the PLL reference clock frequency is automatically calculated for best performance. If you want to specify a different PLL reference clock frequency, uncheck the check box for this parameter.
Clock rate of user logic	PHY_RATE_ENUM	Specifies the relationship between the user logic clock frequency and the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a quarter-rate interface means that the user logic in the FPGA runs at 200MHz.
PLL reference clock frequency	PHY_REF_CLK_FREQ_MHZ	Specifies the PLL reference clock frequency. You must configure this parameter only if you do not check the "Use recommended PLL reference clock frequency" parameter. To configure this parameter, select a valid PLL reference clock frequency from the list. The values in the list can change if you change the memory interface frequency and/or the clock rate of the user logic. For best jitter performance, you should use the fastest possible PLL reference clock frequency.
PLL reference clock jitter	PHY_REF_CLK_JITTER_PS	Specifies the peak-to-peak jitter on the PLL reference clock source. The clock source of the PLL reference clock must meet or exceed the following jitter requirements: 10ps peak to peak, or 1.42ps RMS at 1e-12 BER, 1.22ps at 1e-16 BER.
Specify additional core clocks based on existing PLL	PLL_ADD_EXTRA_CLKS	Displays additional parameters allowing you to create additional output clocks based on the existing PLL. This parameter provides an alternative clock-generation mechanism for when your design exhausts available PLL resources. The additional output clocks that you create can be fed into the core. Clock signals created with this parameter are synchronous to each other, but asynchronous to the memory interface core clock domains (such as emif_usr_clk or afi_clk). You must follow proper clock-domain-crossing techniques when transferring data between clock domains.

Table 242. Group: General / Additional Core Clocks
Display Name	Identifier	Description
Number of additional core clocks	PLL_USER_NUM_OF_EXTRA_CLKS	Specifies the number of additional output clocks to create from the PLL.