External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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7.4.3.5. Arria 10 EMIF IP DDR4 Parameters: Mem Timing

These parameters should be read from the table in the datasheet associated with the speed bin of the memory device (not necessarily the frequency at which the interface is running).
Table 132.  Group: Mem Timing / Parameters dependent on Speed Bin
Display Name Identifier Description
Speed bin MEM_DDR4_SPEEDBIN_ENUM The speed grade of the memory device used. This parameter refers to the maximum rate at which the memory device is specified to run.
TdiVW_total MEM_DDR4_TDIVW_TOTAL_UI TdiVW_total describes the minimum horizontal width of the DQ eye opening required by the receiver (memory device/DIMM). It is measured in UI (1UI = half the memory clock period).
tDQSCK MEM_DDR4_TDQSCK_PS tDQSCK describes the skew between the memory clock (CK) and the input data strobes (DQS) used for reads. It is the time between the rising data strobe edge (DQS, DQS#) relative to the rising CK edge.
tDQSQ MEM_DDR4_TDQSQ_UI tDQSQ describes the latest valid transition of the associated DQ pins for a READ. tDQSQ specifically refers to the DQS, DQS# to DQ skew. It is the length of time between the DQS, DQS# crossing to the last valid transition of the slowest DQ pin in the DQ group associated with that DQS strobe.
tDQSS MEM_DDR4_TDQSS_CYC tDQSS describes the skew between the memory clock (CK) and the output data strobes used for writes. It is the time between the rising data strobe edge (DQS, DQS#) relative to the rising CK edge.
tDSH MEM_DDR4_TDSH_CYC tDSH specifies the write DQS hold time. This is the time difference between the rising CK edge and the falling edge of DQS, measured as a percentage of tCK.
tDSS MEM_DDR4_TDSS_CYC tDSS describes the time between the falling edge of DQS to the rising edge of the next CK transition.
tIH (base) DC level MEM_DDR4_TIH_DC_MV tIH (base) DC level refers to the voltage level which the address/command signal must not cross during the hold window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire hold period.
tIH (base) MEM_DDR4_TIH_PS tIH (base) refers to the hold time for the Address/Command (A) bus after the rising edge of CK. Depending on what AC level the user has chosen for a design, the hold margin can vary (this variance will be automatically determined when the user choses the "tIH (base) AC level").
tINIT MEM_DDR4_TINIT_US tINIT describes the time duration of the memory initialization after a device power-up. After RESET_n is de-asserted, wait for another 500us until CKE becomes active. During this time, the DRAM will start internal initialization; this will be done independently of external clocks.
tIS (base) AC level MEM_DDR4_TIS_AC_MV tIS (base) AC level refers to the voltage level which the address/command signal must cross and remain above during the setup margin window. The signal is considered stable only if it remains above this voltage level (for a logic 1) or below this voltage level (for a logic 0) for the entire setup period.
tIS (base) MEM_DDR4_TIS_PS tIS (base) refers to the setup time for the Address/Command/Control (A) bus to the rising edge of CK.
tMRD MEM_DDR4_TMRD_CK_CYC The mode register set command cycle time, tMRD is the minimum time period required between two MRS commands.
tQH MEM_DDR4_TQH_UI tQH specifies the output hold time for the DQ in relation to DQS, DQS#. It is the length of time between the DQS, DQS# crossing to the earliest invalid transition of the fastest DQ pin in the DQ group associated with that DQS strobe.
tQSH MEM_DDR4_TQSH_CYC tQSH refers to the differential High Pulse Width, which is measured as a percentage of tCK. It is the time during which the DQS is high for a read.
tRAS MEM_DDR4_TRAS_NS tRAS describes the activate to precharge duration. A row cannot be deactivated until the tRAS time has been met. Therefore tRAS determines how long the memory has to wait after a activate command before a precharge command can be issued to close the row.
tRCD MEM_DDR4_TRCD_NS tRCD, row command delay, describes the amount of delay between the activation of a row through the RAS command and the access to the data through the CAS command.
tRP MEM_DDR4_TRP_NS tRP refers to the Precharge (PRE) command period. It describes how long it takes for the memory to disable access to a row by precharging and before it is ready to activate a different row.
tWLH MEM_DDR4_TWLH_PS tWLH describes the write leveling hold time from the rising edge of DQS to the rising edge of CK.
tWLS MEM_DDR4_TWLS_PS tWLS describes the write leveling setup time. It is measured from the rising edge of CK to the rising edge of DQS.
tWR MEM_DDR4_TWR_NS tWR refers to the Write Recovery time. It specifies the amount of clock cycles needed to complete a write before a precharge command can be issued.
VdiVW_total MEM_DDR4_VDIVW_TOTAL VdiVW_total describes the Rx Mask voltage, or the minimum vertical width of the DQ eye opening required by the receiver (memory device/DIMM). It is measured mV.
Table 133.  Group: Mem Timing / Parameters dependent on Speed Bin, Operating Frequency, and Page Size
Display Name Identifier Description
tCCD_L MEM_DDR4_TCCD_L_CYC tCCD_L refers to the CAS_n-to-CAS_n delay (long). It is the minimum time interval between two read/write (CAS) commands to the same bank group.
tCCD_S MEM_DDR4_TCCD_S_CYC tCCD_S refers to the CAS_n-to-CAS_n delay (short). It is the minimum time interval between two read/write (CAS) commands to different bank groups.
tFAW_dlr MEM_DDR4_TFAW_DLR_CYC tFAW_dlr refers to the four activate window to different logical ranks. It describes the period of time during which only four banks can be active across all logical ranks within a 3DS DDR4 device.
tFAW MEM_DDR4_TFAW_NS tFAW refers to the four activate window time. It describes the period of time during which only four banks can be active.
tRRD_dlr MEM_DDR4_TRRD_DLR_CYC tRRD_dlr refers to the Activate to Activate Command Period to Different Logical Ranks. It is the minimum time interval (measured in memory clock cycles) between two activate commands to different logical ranks within a 3DS DDR4 device.
tRRD_L MEM_DDR4_TRRD_L_CYC tRRD_L refers to the Activate to Activate Command Period (long). It is the minimum time interval (measured in memory clock cycles) between two activate commands to the same bank group.
tRRD_S MEM_DDR4_TRRD_S_CYC tRRD_S refers to the Activate to Activate Command Period (short). It is the minimum time interval between two activate commands to the different bank groups.
tRTP MEM_DDR4_TRTP_CYC tRTP refers to the internal READ Command to PRECHARGE Command delay. It is the number of memory clock cycles that is needed between a read command and a precharge command to the same rank.
tWTR_L MEM_DDR4_TWTR_L_CYC tWTR_L or Write Timing Parameter describes the delay from start of internal write transaction to internal read command, for accesses to the same bank group. The delay is measured from the first rising memory clock edge after the last write data is received to the rising memory clock edge when a read command is received.
tWTR_S MEM_DDR4_TWTR_S_CYC tWTR_S or Write Timing Parameter describes the delay from start of internal write transaction to internal read command, for accesses to the different bank group. The delay is measured from the first rising memory clock edge after the last write data is received to the rising memory clock edge when a read command is received.
Table 134.  Group: Mem Timing / Parameters dependent on Density and Temperature
Display Name Identifier Description
tREFI MEM_DDR4_TREFI_US tREFI refers to the average periodic refresh interval. It is the maximum amount of time the memory can tolerate in between each refresh command
tRFC_dlr MEM_DDR4_TRFC_DLR_NS tRFC_dlr refers to the Refresh Cycle Time to different logical rank. It is the amount of delay after a refresh command to one logical rank before an activate command can be accepted by another logical rank within a 3DS DDR4 device. This parameter is dependent on the memory density and is necessary for proper hardware functionality.
tRFC MEM_DDR4_TRFC_NS tRFC refers to the Refresh Cycle Time. It is the amount of delay after a refresh command before an activate command can be accepted by the memory. This parameter is dependent on the memory density and is necessary for proper hardware functionality.

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