External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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7.4.3.3. Arria 10 EMIF IP DDR4 Parameters: Mem I/O

Table 125.  Group: Mem I/O / Memory I/O Settings
Display Name Identifier Description
DB Host Interface DQ Driver MEM_DDR4_DB_DQ_DRV_ENUM Specifies the driver impedance setting for the host interface of the data buffer. This parameter determines the value of the control word BC03 of the data buffer. Perform board simulation to obtain the optimal value for this setting.
DB Host Interface DQ RTT_NOM MEM_DDR4_DB_RTT_NOM_ENUM Specifies the RTT_NOM setting for the host interface of the data buffer. Only "RTT_NOM disabled" is supported. This parameter determines the value of the control word BC00 of the data buffer.
DB Host Interface DQ RTT_PARK MEM_DDR4_DB_RTT_PARK_ENUM Specifies the RTT_PARK setting for the host interface of the data buffer. This parameter determines the value of control word BC02 of the data buffer. Perform board simulation to obtain the optimal value for this setting.
DB Host Interface DQ RTT_WR MEM_DDR4_DB_RTT_WR_ENUM Specifies the RTT_WR setting of the host interface of the data buffer. This parameter determines the value of the control word BC01 of the data buffer. Perform board simulation to obtain the optimal value for this setting.
Use recommended initial VrefDQ value MEM_DDR4_DEFAULT_VREFOUT Specifies to use the recommended initial VrefDQ value. This value is used as a starting point and may change after calibration.
Output drive strength setting MEM_DDR4_DRV_STR_ENUM Specifies the output driver impedance setting at the memory device. To obtain optimum signal integrity performance, select option based on board simulation results.
RCD CA Input Bus Termination MEM_DDR4_RCD_CA_IBT_ENUM Specifies the input termination setting for the following pins of the registering clock driver: DA0..DA17, DBA0..DBA1, DBG0..DBG1, DACT_n, DC2, DPAR. This parameter determines the value of bits DA[1:0] of control word RC7x of the registering clock driver. Perform board simulation to obtain the optimal value for this setting.
RCD DCKE Input Bus Termination MEM_DDR4_RCD_CKE_IBT_ENUM Specifies the input termination setting for the following pins of the registering clock driver: DCKE0, DCKE1. This parameter determines the value of bits DA[5:4] of control word RC7x of the registering clock driver. Perform board simulation to obtain the optimal value for this setting.
RCD DCS[3:0]_n Input Bus Termination MEM_DDR4_RCD_CS_IBT_ENUM Specifies the input termination setting for the following pins of the registering clock driver: DCS[3:0]_n. This parameter determines the value of bits DA[3:2] of control word RC7x of the registering clock driver. Perform board simulation to obtain the optimal value for this setting.
RCD DODT Input Bus Termination MEM_DDR4_RCD_ODT_IBT_ENUM Specifies the input termination setting for the following pins of the registering clock driver: DODT0, DODT1. This parameter determines the value of bits DA[7:6] of control word RC7x of the registering clock driver. Perform board simulation to obtain the optimal value for this setting.
ODT Rtt nominal value MEM_DDR4_RTT_NOM_ENUM Determines the nominal on-die termination value applied to the DRAM. The termination is applied any time that ODT is asserted. If you specify a different value for RTT_WR, that value takes precedence over the values mentioned here. For optimum signal integrity performance, select your option based on board simulation results.
RTT PARK MEM_DDR4_RTT_PARK If set, the value is applied when the DRAM is not being written AND ODT is not asserted HIGH.
Dynamic ODT (Rtt_WR) value MEM_DDR4_RTT_WR_ENUM Specifies the mode of the dynamic on-die termination (ODT) during writes to the memory device (used for multi-rank configurations). For optimum signal integrity performance, select this option based on board simulation results.
RCD and DB Manufacturer (LSB) MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB Specifies the LSB of the ID code of the registering clock driver and data buffer manufacturer. The value must come from Byte 133 of the SPD from the DIMM vendor.
RCD and DB Manufacturer (MSB) MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB Specifies the MSB of the ID code of the registering clock driver and data buffer manufacturer. The value must come from Byte 134 of the SPD from the DIMM vendor.
RCD Revision Number MEM_DDR4_SPD_135_RCD_REV Specifies the die revision of the registering clock driver. The value must come from Byte 135 of the SPD from the DIMM vendor.
SPD Byte 137 - RCD Drive Strength for Command/Address MEM_DDR4_SPD_137_RCD_CA_DRV Specifies the drive strength of the registering clock driver's control and command/address outputs to the DRAM. The value must come from Byte 137 of the SPD from the DIMM vendor.
SPD Byte 138 - RCD Drive Strength for CK MEM_DDR4_SPD_138_RCD_CK_DRV Specifies the drive strength of the registering clock driver's clock outputs to the DRAM. The value must come from Byte 138 of the SPD from the DIMM vendor.
DB Revision Number MEM_DDR4_SPD_139_DB_REV Specifies the die revision of the data buffer. The value must come from Byte 139 of the SPD from the DIMM vendor.
SPD Byte 140 - DRAM VrefDQ for Package Rank 0 MEM_DDR4_SPD_140_DRAM_VREFDQ_R0 Specifies the VrefDQ setting for package rank 0 of an LRDIMM. The value must come from Byte 140 of the SPD from the DIMM vendor.
SPD Byte 141 - DRAM VrefDQ for Package Rank 1 MEM_DDR4_SPD_141_DRAM_VREFDQ_R1 Specifies the VrefDQ setting for package rank 1 of an LRDIMM. The value must come from Byte 141 of the SPD from the DIMM vendor.
SPD Byte 142 - DRAM VrefDQ for Package Rank 2 MEM_DDR4_SPD_142_DRAM_VREFDQ_R2 Specifies the VrefDQ setting for package rank 2 (if it exists) of an LRDIMM. The value must come from Byte 142 of the SPD from the DIMM vendor.
SPD Byte 143 - DRAM VrefDQ for Package Rank 3 MEM_DDR4_SPD_143_DRAM_VREFDQ_R3 Specifies the VrefDQ setting for package rank 3 (if it exists) of an LRDIMM. The value must come from Byte 143 of the SPD from the DIMM vendor.
SPD Byte 144 - DB VrefDQ for DRAM Interface MEM_DDR4_SPD_144_DB_VREFDQ Specifies the VrefDQ setting of the data buffer's DRAM interface. The value must come from Byte 144 of the SPD from the DIMM vendor.
SPD Byte 145-147 - DB MDQ Drive Strength and RTT MEM_DDR4_SPD_145_DB_MDQ_DRV Specifies the drive strength of the MDQ pins of the data buffer's DRAM interface. The value must come from either Byte 145 (data rate = 1866), 146 (1866 data rate = 2400), or 147 (2400 data rate = 3200) of the SPD from the DIMM vendor.
SPD Byte 148 - DRAM Drive Strength MEM_DDR4_SPD_148_DRAM_DRV Specifies the drive strength of the DRAM. The value must come from Byte 148 of the SPD from the DIMM vendor.
SPD Byte 149-151 - DRAM ODT (RTT_WR and RTT_NOM) MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM Specifies the RTT_WR and RTT_NOM setting of the DRAM. The value must come from either Byte 149 (data rate = 1866), 150 (1866 data rate = 2400), or 151 (2400 data rate = 3200) of the SPD from the DIMM vendor.
SPD Byte 152-154 - DRAM ODT (RTT_PARK) MEM_DDR4_SPD_152_DRAM_RTT_PARK Specifies the RTT_PARK setting of the DRAM. The value must come from either Byte 152 (data rate = 1866), 153 (1866 data rate = 2400), or 154 (2400 data rate = 3200) of the SPD from the DIMM vendor.
VrefDQ training range MEM_DDR4_VREFDQ_TRAINING_RANGE VrefDQ training range.
VrefDQ training value MEM_DDR4_VREFDQ_TRAINING_VALUE VrefDQ training value.
Table 126.  Group: Mem I/O / ODT Activation
Display Name Identifier Description
Use Default ODT Assertion Tables MEM_DDR4_USE_DEFAULT_ODT Enables the default ODT assertion pattern as determined from vendor guidelines. These settings are provided as a default only; you should simulate your memory interface to determine the optimal ODT settings and assertion patterns.

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