External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.4.3.12. Additional Notes About Parameterizing Arria 10 EMIF IP for HPS7.4.4.12. Additional Notes About Parameterizing Arria 10 EMIF IP for HPS

Although Arria 10 EMIF IP and Arria 10 EMIF IP for HPS are similar components, there are some additional requirements necessary in the HPS case.

The following rules and restrictions apply to Arria 10 EMIF IP for HPS:

  • Supported memory protocols are limited to DDR3 and DDR4.
  • The only supported configuration is the hard PHY with the hard memory controller.
  • The maximum memory clock frequency for Arria 10 EMIF IP for HPS may be different than for regular Arria 10 EMIF IP. Refer to the External Memory Interface Spec Estimator for details.
  • Only half-rate interfaces are supported.
  • Sharing of clocks is not supported.
  • The total interface width is limited to a multiple of 16, 24, 40 or 72 bits (with ECC enabled), or a positive value divisible by the number of DQ pins per DQS group (with ECC not enabled). For devices other than 10ASXXXKX40, the total interface width is further limited to a maximum of 40 bits with ECC enabled and 32 bits with ECC not enabled.
  • Only x8 data groups are supported; that is, DQ pins-per-DQS group must be 8.
  • DM pins must be enabled.
  • The EMIF debug toolkit is not supported.
  • Ping Pong PHY is not supported.
  • The interface to and from the HPS is a fixed-width conduit.
  • A maximum of 3 address/command I/O lanes are supported. For example:
    • DDR3
      • For component format, maximum number of chip selects is 2.
      • For UDIMM or SODIMM format:
        • Maximum number of DIMMs is 2, when the number of physical ranks per DIMM is 1.
        • Maximum number of DIMMs is 1, when the number of physical ranks per DIMM is 2.
        • Maximum number of physical ranks per DIMMs is 2, when the number of DIMMs is 1.
      • For RDIMM format:
        • Maximum number of clocks is 1.
        • Maximum number of DIMMs is 1.
        • Maximum number of physical ranks per DIMM is 2.
      • LRDIMM memory format is not supported.
    • DDR4
      • For component format:
        • Maximum number of clocks is 1.
        • Maximum number of chip selects is 2
      • For UDIMM or RDIMM format:
        • Maximum number of clocks is 1.
        • Maximum number of DIMMs is 2, when the number of physical ranks per DIMM is 1.
        • Maximum number of DIMMs is 1, when the number of physical ranks per DIMM is 2.
        • Maximum number of physical ranks per DIMM is 2, when the number of DIMMs is 1.
      • For SODIMM format:
        • Maximum number of clocks is 1.
        • Maximum number of DIMMs is 1.
        • Maximum number of physical ranks per DIMM is 1.
  • Arria 10 EMIF IP for HPS also has specific pin-out requirements. For information, refer to Planning Pin and FPGA Resources.

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