LDPC IP Core User Guide

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ID 683381
Date 4/04/2022
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 2. LDPC IP EOL 2. About the LDPC IP Core 3. Getting Started with the LDPC IP Core 4. LDPC IP Core Specifications 5. Document Revision History A. LDPC IP Core Document Archive
2. About the LDPC IP Core x
2.1. LDPC IP Core Features 2.2. LDPC IP Device Family Support 2.3. LDPC IP Core Release Information 2.4. DSP Intel® FPGA IP Verification 2.5. LDPC IP Core Performance
3. Getting Started with the LDPC IP Core x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. IP Catalog and Parameter Editor 3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 3.4. Simulating Intel® FPGA IP Cores
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode 3.1.2. LDPC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
3.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. LDPC IP Core Specifications x
4.1. LDPC IP Core Interfaces 4.2. LDPC IP Core Parameters
4.1. LDPC IP Core Interfaces x
4.1.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.1.2. Clock and Reset Interfaces 4.1.3. LDPC IP Core Signals
4.1.3. LDPC IP Core Signals x
4.1.3.1. LDPC IP Core Backpressure
Product Discontinuance Notification
2. LDPC IP EOL
2. About the LDPC IP Core
3. Getting Started with the LDPC IP Core
4. LDPC IP Core Specifications
5. Document Revision History
A. LDPC IP Core Document Archive

3.1.1. Avalon-ST Interfaces in DSP IP Cores

Avalon-ST interfaces define a standard, flexible, and modular protocol for data transfers from a source interface to a sink interface.

The input interface is an Avalon-ST sink and the output interface is an Avalon-ST source. The Avalon-ST interface supports packet transfers with packets interleaved across multiple channels.

Avalon-ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries. Such interfaces typically contain data, ready, and valid signals. Avalon-ST interfaces can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels. The Avalon-ST interface inherently synchronizes multichannel designs, which allows you to achieve efficient, time-multiplexed implementations without having to implement complex control logic.

Avalon-ST interfaces support backpressure, which is a flow control mechanism where a sink can signal to a source to stop sending data. The sink typically uses backpressure to stop the flow of data when its FIFO buffers are full or when it has congestion on its output.

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