FFT IP Core: User Guide

Download PDF
ID 683374
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. FFT IP Core Getting Started 3. FFT IP Core Functional Description 4. Block Floating Point Scaling 5. Document Revision History A. FFT IP Core User Guide Document Archive
1. About This IP Core x
1.1. Intel® DSP IP Core Features 1.2. FFT IP Core Features 1.3. General Description 1.4. DSP IP Core Device Family Support 1.5. DSP IP Core Verification 1.6. FFT IP Core Release Information 1.7. Performance and Resource Utilization
1.3. General Description x
1.3.1. Fixed Transform Size FFT 1.3.2. Variable Streaming FFT
2. FFT IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.5. Simulating Intel® FPGA IP Cores 2.6. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FFT IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.5. Simulating Intel® FPGA IP Cores x
2.5.1. Simulating the Fixed-Transform FFT IP Core in the MATLAB Software 2.5.2. Simulating the Variable Streaming FFT IP Core in the MATLAB Software
3. FFT IP Core Functional Description x
3.1. Fixed Transform FFTs 3.2. Variable Streaming FFTs 3.3. FFT Processor Engines 3.4. I/O Data Flow 3.5. FFT IP Core Parameters 3.6. FFT IP Core Interfaces and Signals
3.2. Variable Streaming FFTs x
3.2.1. Fixed-Point Variable Streaming FFTs 3.2.2. Floating-Point Variable Streaming FFTs
3.3. FFT Processor Engines x
3.3.1. Quad-Output FFT Engine 3.3.2. Single-Output FFT Engine
3.4. I/O Data Flow x
3.4.1. Streaming FFT 3.4.2. Variable Streaming 3.4.3. Buffered Burst 3.4.4. Burst
3.4.1. Streaming FFT x
3.4.1.1. Using the Streaming FFT 3.4.1.2. Changing the Direction on a Block-by-Block Basis 3.4.1.3. Enabling the Streaming FFT
3.4.2. Variable Streaming x
3.4.2.1. Changing Block Size 3.4.2.2. Changing Direction 3.4.2.3. I/O Order 3.4.2.4. Enabling the Variable Streaming FFT 3.4.2.5. Dynamically Changing the FFT Size 3.4.2.6. I/O Order
3.4.3. Buffered Burst x
3.4.3.1. Enabling the Buffered Burst FFT
3.6. FFT IP Core Interfaces and Signals x
3.6.1. Avalon-ST Interfaces in DSP IP Cores 3.6.2. FFT IP Core Avalon-ST Signals
3.6.2. FFT IP Core Avalon-ST Signals x
3.6.2.1. Component Specific Signals
4. Block Floating Point Scaling x
4.1. Possible Exponent Values 4.2. Implementing Scaling 4.3. Unity Gain in an IFFT+FFT Pair
4.2. Implementing Scaling x
4.2.1. Example of Scaling
1. About This IP Core
2. FFT IP Core Getting Started
3. FFT IP Core Functional Description
4. Block Floating Point Scaling
5. Document Revision History
A. FFT IP Core User Guide Document Archive

2.3.1. Files Generated for Altera IP Cores and Qsys Systems

The software generates the following output file structure for IP cores and Qsys systems. For Arria 10 devices and newer, the generated .qsys file must be added to your project to represent IP and Qsys systems. For devices released prior to Arria 10 devices, the generated .qip and .sip files must be added to your project to represent IP and Qsys systems. The software generates the following output file structure for IP cores and Qsys systems. The generated .qsys file must be added to your project to represent IP and Qsys systems.
Figure 3. Files generated for IP cores and Qsys Systems


Table 4.  IP Core and Qsys Simulation Generated Files

File Name

Description

<my_ip>.qsys

The Qsys system or top-level IP variation file. <my_ip> is the name that you give your IP variation. You must add the .qsys file to your Quartus project to enable NativeLink for Arria 10 and Stratix 10 device families.

The Qsys system or top-level IP variation file. <my_ip> is the name that you give your IP variation.

<system>.sopcinfo

Describes the connections and IP component parameterizations in your Qsys system. You can parse its contents to get requirements when you develop software drivers for IP components.

Downstream tools such as the Nios II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.

<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.
<my_ip>.html

A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<my_ip>_generation.rpt IP or Qsys generation log file. A summary of the messages during IP generation.
<my_ip>.debuginfo Contains post-generation information. Used to pass System Console and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect.
<my_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the software.

<my_ip>.csv Contains information about the upgrade status of the IP component.

<my_ip>.bsf

A Block Symbol File (.bsf) representation of the IP variation for use in Block Diagram Files (.bdf).

<my_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<my_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
<my_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.
<my_ip>.sip Contains information required for NativeLink simulation of IP components. You must add the .sip file to your Quartus project to enable NativeLink for Arria II, Arria V, Cyclone IV, Cyclone V, MAX 10, MAX II, MAX V, Stratix IV, and Stratix V devices.
<my_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<my_ip>.regmap If the IP contains register information, the .regmap file generates. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in System Console.
<my_ip>.svd

Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system.

During synthesis, the .svd files for slave interfaces visible to System Console masters are stored in the .sof file in the debug section. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name.

<my_ip>.v

or

<my_ip>.vhd 		HDL files that instantiate each submodule or child IP core for synthesis or simulation.
mentor/

Contains a ModelSim® script msim_setup.tcl to set up and run a simulation.

aldec/

Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation.

/synopsys/vcs

/synopsys/vcsmx

Contains a shell script vcs_setup.sh to set up and run a VCS® simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX® simulation.

/cadence

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.

/submodules Contains HDL files for the IP core submodule.
<IP submodule>/ For each generated IP submodule directory, Qsys generates /synth and /sim sub-directories.
Level Two Title