100G Interlaken Intel® FPGA IP User Guide

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ID 683338
Date 9/20/2022
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Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. Getting Started With the 100G Interlaken IP Core 3. 100G Interlaken IP Core Parameter Settings 4. Functional Description 5. 100G Interlaken IP core Signals 6. 100G Interlaken IP Core Register Map 7. 100G Interlaken IP Core Test Features 8. Advanced Parameter Settings 9. Out-of-Band Flow Control in the 100G Interlaken IP core 10. 100G Interlaken IP core User Guide Archives 11. Document Revision History for 100G Interlaken User Guide A. Performance and Fmax Requirements for 100G Ethernet Traffic
1. About This IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grade Support 1.6. Release Information
1.1. Features x
1.1.1. IP Core Supported Combinations of Number of Lanes and Data Rate 1.1.2. IP Core Theoretical Raw Aggregate Bandwidth
2. Getting Started With the 100G Interlaken IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 100G Interlaken IP Core Parameters and Options 2.3. Files Generated for Arria V GZ and Stratix V Variations 2.4. Files Generated for Intel® Arria® 10 Variations 2.5. Simulating the 100G Interlaken IP Core 2.6. Integrating Your IP Core in Your Design 2.7. Compiling the Full Design and Programming the FPGA 2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. Transceiver Logical Channel Numbering 2.6.3. Adding the Reconfiguration Controller 2.6.4. Adding the External PLL
2.6.3. Adding the Reconfiguration Controller x
2.6.3.1. Generating the Reconfiguration Controller 2.6.3.2. Connecting the Reconfiguration Controller to the IP Core
3. 100G Interlaken IP Core Parameter Settings x
3.1. Number of Lanes 3.2. Meta Frame Length in Words 3.3. Data Rate 3.4. Transceiver Reference Clock Frequency 3.5. Include Advanced Error Reporting and Handling 3.6. Enable M20K ECC Support 3.7. Include Diagnostic Features 3.8. Enable Native PHY Debug Master Endpoint (NPDME) 3.9. Include In-Band Flow Control Block 3.10. Number of Calendar Pages 3.11. TX Scrambler Seed 3.12. Transfer Mode Selection 3.13. Data Format
4. Functional Description x
4.1. Interfaces Overview 4.2. High Level Block Diagram 4.3. Clocking and Reset Structure for IP Core 4.4. Interleaved and Packet Modes 4.5. Dual Segment Mode 4.6. M20K ECC Support 4.7. 100G Interlaken IP Core Transmit Path 4.8. 100G Interlaken IP Core Receive Path
4.1. Interfaces Overview x
4.1.1. Application Interface 4.1.2. Interlaken Interface 4.1.3. Out‑of‑Band Flow Control Interface 4.1.4. Management Interface 4.1.5. Transceiver Control Interfaces
4.1.5. Transceiver Control Interfaces x
4.1.5.1. Transceiver Reconfiguration Controller Interface 4.1.5.2. Intel® Arria® 10 External PLL Interface 4.1.5.3. Intel® Arria® 10 Transceiver Reconfiguration Interface
4.3. Clocking and Reset Structure for IP Core x
4.3.1. 100G Interlaken IP Core Clock Signals 4.3.2. IP Core Reset 4.3.3. IP Core Reset Sequence with the Reconfiguration Controller
4.7. 100G Interlaken IP Core Transmit Path x
4.7.1. 100G Interlaken IP Core Transmit User Data Interface Examples 4.7.2. 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side 4.7.3. 100G Interlaken IP Core Transmit Path Blocks
4.7.1. 100G Interlaken IP Core Transmit User Data Interface Examples x
4.7.1.1. 100G Interlaken IP Core Interleaved Mode (Segmented Mode) Example 4.7.1.2. 100G Interlaken IP Core Packet Mode Operation Example 4.7.1.3. 100G Interlaken IP Core Back-Pressured Packet Transfer Example 4.7.1.4. 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit Example
4.7.3. 100G Interlaken IP Core Transmit Path Blocks x
4.7.3.1. 100G Interlaken IP Core TX Transmit Buffer 4.7.3.2. 100G Interlaken IP Core TX MAC 4.7.3.3. 100G Interlaken IP Core TX PCS 4.7.3.4. 100G Interlaken IP Core TX PMA
4.8. 100G Interlaken IP Core Receive Path x
4.8.1. 100G Interlaken IP Core Receive User Data Interface Examples 4.8.2. 100G Interlaken IP Core RX Errored Packet Handling 4.8.3. In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data Interface 4.8.4. 100G Interlaken IP Core Receive Path Blocks
4.8.1. 100G Interlaken IP Core Receive User Data Interface Examples x
4.8.1.1. 100G Interlaken IP Core Receiver Side Example 4.8.1.2. 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive Example
4.8.2. 100G Interlaken IP Core RX Errored Packet Handling x
4.8.2.1. 100G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
4.8.4. 100G Interlaken IP Core Receive Path Blocks x
4.8.4.1. 100G Interlaken IP Core RX PMA 4.8.4.2. 100G Interlaken IP Core RX PCS 4.8.4.3. 100G Interlaken IP Core RX MAC 4.8.4.4. 100G Interlaken IP Core RX Regroup Block
5. 100G Interlaken IP core Signals x
5.1. 100G Interlaken IP Core Clock Interface Signals 5.2. 100G Interlaken IP Core Reset Interface Signals 5.3. 100G Interlaken IP Core User Data Transfer Interface Signals 5.4. 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals 5.5. 100G Interlaken IP Core Management Interface 5.6. Device Dependent Signals
5.6. Device Dependent Signals x
5.6.1. Transceiver Reconfiguration Controller Interface Signals 5.6.2. Intel® Arria® 10 External PLL Interface Signals 5.6.3. Intel® Arria® 10 Transceiver Reconfiguration Interface Signals
7. 100G Interlaken IP Core Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode 7.3. PRBS Generation and Validation 7.4. CRC32 Error Injection 7.5. CRC24 Error Injection
7.3. PRBS Generation and Validation x
7.3.1. Setting up PRBS Mode in Arria V and Stratix V Devices 7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices
8. Advanced Parameter Settings x
8.1. Hidden Parameters 8.2. Modifying Hidden Parameter Values
8.1. Hidden Parameters x
8.1.1. Include Temp Sense 8.1.2. RXFIFO Address Width 8.1.3. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)
9. Out-of-Band Flow Control in the 100G Interlaken IP core x
9.1. Out-of-Band Flow Control Block Clocks 9.2. TX Out‑of‑Band Flow Control Signals 9.3. RX Out-of-Band Flow Control Signals
1. About This IP Core
2. Getting Started With the 100G Interlaken IP Core
3. 100G Interlaken IP Core Parameter Settings
4. Functional Description
5. 100G Interlaken IP core Signals
6. 100G Interlaken IP Core Register Map
7. 100G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 100G Interlaken IP core
10. 100G Interlaken IP core User Guide Archives
11. Document Revision History for 100G Interlaken User Guide
A. Performance and Fmax Requirements for 100G Ethernet Traffic

B.2. Document Revision History for 100G Interlaken Intel® FPGA IP User Guide

Table 35.  100G Interlaken IP core User Guide Revision History

Date

ACDS Version

IP Version

Changes Made

2019.07.12 19.2 19.2.0
  • Rebranded the document as per Intel standards.
  • Renamed the parameter Enable Native XCVR PHY ADME to Enable Native PHY Debug Master Endpoint (NPDME).
  • Changed the document title from 100G Interlaken MegaCore Function User Guide to 100G Interlaken Intel FPGA IP User Guide.
  • Renamed MegaCore to Intel FPGA IP.
2018.03.05 16.0 16.0 Corrected bit range of reconfig_address signal in Intel® Arria® 10 Transceiver Reconfiguration Interface Signals section.
2016.05.02 16.0 16.0
  • Added a new topic titled Creating a SignalTap II Debug File to Match Your Design Hierarchy.
  • Removed callouts to set_global_assignment -name DISABLE_EMBEDDED_TIMING_CONSTRAINT ON .
  • Removed the chapter Arria 10 Hardware Example Design and 100G Interlaken IP Core Testbench, instead refer to the 100G Interlaken Example Design User Guide.
2015.11.02 15.1 15.1
  • Updated for new Quartus Prime software v15.1 release.
  • Added new Enable Native XCVR PHY ADME parameter for Intel® Arria® 10 variations.
  • Updated behavior of irx_err signal. In previous releases, this signal was asserted synchronously with irx_eop. Now it is asserted synchronously with irx_eob, and is only asserted if the IP core can identify the burst with which the error is associated.
  • Updated with change in process to generate legacy testbench.
  • Added new Intel® Arria® 10 hardware example design.
  • Updated generated directory structure for non- Intel® Arria® 10 variations and location of testbench files for all variations.
  • Corrected descriptions of TX out-of-band flow control interface signals fc_clk, fc_data, and fc_sync to indicate they are intended to connect to an upstream RX out-of-band block rather than a downstream block.
  • Corrected 100G Interlaken IP Core Transceiver Initialization Sequence figure. Corrected descriptions of use of reset_n signal to indicate user must assert (low) and deassert (raise) the signal to initiate the reset sequence.
2015.05.04 15.0 15.0
  • Added new TX scrambler seed parameter in new section. Previously this parameter was hidden (SCRAM_CONST) and unavailable for Intel® Arria® 10 devices. In the IP core version 15.0 and later, you must modify the scrambler seed from the parameter editor.
  • Improved description of itx_ifc_err output signal.
  • Improved description of itx_hungry output signal.
  • Updated filenames for hidden parameter editing to include the filenames for Intel® Arria® 10 variations.

2014.12.15

14.1

 14.1
  • Updated release-specific information for the software release v14.1, including new resource utilization numbers and new Intel® Arria® 10 speed grade notation.
  • Updated for new Quartus II IP Catalog, which replaces the MegaWizard Plug-In Manager starting in the Quartus II software v14.0. Changes are located primarily in Getting Started With the 100G Interlaken IP Core chapter. Reordered the chapter to accommodate the new descriptions.
  • Fixed speed grade information for Intel® Arria® 10 devices in Device Speed Grade Support section.
  • Removed mm_clk_locked signal. Signal is removed in the IP core v14.0 and later.
  • Corrected management interface read operation waveform and requirements. In the IP core v13.1 and later, the read data is valid two cycles after mm_read is asserted, not one cycle as was previously shown.
  • Corrected instructions to connect the external TX PLL to include the tx_cal_busy signal, and added example figure to illustrate the required connections between the IP core and an ATX PLL. Changes are located in Adding the External PLL section.
  • In relevant parameter description sections, removed note to ignore the compilation warnings if you turn off any of the following parameters. The issue is fixed in the SDC file in the IP core version 14.0 and later.
    • Include advanced error reporting and handling
    • Enable M20K ECC support
    • Include diagnostic features
    • Include in-band flow control functionality
  • Removed CNTR_BITS RTL parameter. Parameter is removed in the IP core v14.0 and later.
  • Added information to IP Core Reset section about the current required wait from reset to successful register access in IP Core Reset section.
  • Corrected width of reconfig_waitrequest signal to one bit. This signal has been a single bit in all versions that support Arria 10 devices, starting with the IP core version 13.1 Intel® Arria® 10 Edition.
  • Corrected the text that describes the trade-offs between enabling and disabling the Enable M20K ECC support parameter.
  • Added information about turning on and off loopback mode in two new sections, External Loopback Mode and Internal Serial Loopback Mode, in IP Core Test Features chapter.
  • Clarified that the testbench and example design are generated only if you specify the IP core synthesis and simulation models are in Verilog HDL. The IP core does not support VHDL models, despite the fact that in the IP core v14.0 and later, the parameter editor appears to offer that option.
  • Fixed assorted typos and formatting issues.

December 2013

13.1 Intel® Arria® 10 Edition (2013.12. 02)

13.1
  • Added preliminary support for Intel® Arria® 10 devices.
  • Documented features of new Intel® Arria® 10 variations:
    • User logic must configure external PLLs.
    • IP core includes reconfiguration controller.
    • IP core includes new Avalon-MM interface to program Intel® Arria® 10 Native PHY IP core registers.
    • IP core does not support all of the hidden parameters.
    • IP core does not support temperature register and other registers related to unsupported parameters.
    • IP core provides a different process to enable the PRBS and CRC32 error injection testing features in Intel® Arria® 10 variations.
  • Corrected recommended simulation value for Meta frame length in words parameter, from 64 (an unsupported value) to 128 (the minimum supported value).

November 2013

13.1 (2013.11.04)

13.1
  • Documented change from Received data format to Data format parameter. If you select Single segment mode, the IP core can no longer handle incoming dual segment traffic on the TX client data interface.
  • Added information about the four new parameters:
    • Include advanced error reporting and handling
    • Enable M20K ECC support
    • Include diagnostic features
    • Include in-band flow control functionality
  • Documented new ECC feature for Intel® Arria® 10 and Stratix V device M20K memory blocks, including four new registers:
    • CNT_ERR_TX
    • CNT_UNCOR_TX
    • CNT_ERR_RX
    • CNT_UNCOR_RX
  • Documented new diagnostic feature: CRC24 error injection, including the new ERR_INJECT register.
  • Added resource utilization information.
  • Updated IP core generation instructions to indicate the MegaWizard Plug-In Manager no longer prompts the user to generate or not generate the example design. Instead, the example design is generated in all cases.
  • Provided additional information about TEMP_SENSE register.
  • Corrected typo in width of itx_hungry signal.
  • Added OpenCore Plus feature support in Installation and Licensing section.

May 2013

13.0

(2013.05.06)

13.0
  • Documented the new dual segment mode, including:
    • New Received data format parameter in the 100G Interlaken parameter editor.
    • Changed user data transfer signal widths.
    • Added new itx_ifc_err signal.
    • Expanded Fmax requirements discussion to include the dual segment mode case.
  • Documented the new Transfer mode selection parameter in the 100G Interlaken parameter editor. Previously this parameter was hidden (TX_PKTMOD_ONLY).
  • Documented new error handling features, including changes to and renaming of irx_crc_24_err signal to irx_err.
  • Added PRBS support. Changes include addition of new hard PCS registers.
  • Added support for CRC-32 error injection.
  • Updated device speed grade information.
  • Modified document format.

February 2013

12.1 SP1

12.1 SP1
  • Reformatted figures.
  • Modified Figure 4–1 on page 4–2, Figure 4–2 on page 4–4, Figure 5–1 on page 5–10, and Figure 5–2 on page 5–10 for readability.
  • Removed mention of OpenCore evaluation feature from “100G Interlaken IP Core Evaluation Features” on page 1–5 because the feature name caused confusion with the OpenCore Plus evaluation feature. The current and past descriptions of the evaluation features are correct.
  • Added default parameter values in Chapter 3, Parameter Settings and in Chapter 7, Advanced Parameter Settings.
  • Renamed Appendix A, Performance and Fmax Requirements for 100G Ethernet Traffic.
  • Consolidated information about 100G Interlaken MegaCore function license. All variations of this IP core are available if you have a single Intel® license for this IP core.
  • Enhanced description of RX and TX data paths in new sections “Transmit Path Blocks” on page 4–9 and “Receive Path Blocks” on page 4–13.
  • Corrected location of “Receiver Side Timing Diagrams” on page 4–10 to “Receive Path” on page 4–10.

November 2012

12.1

12.1

Initial release.

Level Two Title