Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Download
ID 683301
Date 4/19/2023
Public
Document Table of Contents
Document Table of Contents x
Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

HPS Power Supply Operating Conditions

Table 12.  HPS Power Supply Operating Conditions for Intel® Agilex™ Devices

This table lists the steady-state voltage and current values expected for Intel® Agilex™ system-on-a-chip (SoC) devices with ARM-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions for Intel® Agilex™ Devices table for the steady-state voltage values expected from the FPGA portion of the Intel® Agilex™ SoC devices.

For specification status, see the Data Sheet Status table

Symbol Description Condition Minimum Typical Maximum Unit
VCCL_HPS HPS core voltage and periphery circuitry power supply Performance boost, fixed voltage: –1V (Typical) – 3% 0.95 (Typical) + 3% V
SmartVID: –1V, –2V, –3V, –3E 22 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4F, –4X 0.776 0.8 0.824 V
VCCPLLDIG_HPS HPS PLL digital power supply (can be connected to VCCL_HPS) Performance boost, fixed voltage: –1V (Typical) – 3% 0.95 (Typical) + 3% V
SmartVID: –1V, –2V, –3V, –3E 22 (Typical) – 3% 0.70 – 0.90 (Typical) + 3% V
Fixed voltage: –4F, –4X 0.776 0.8 0.824 V
VCCPLL_HPS HPS PLL analog power supply 1.8 V 1.71 1.8 1.89 V
VCCIO_HPS HPS I/O buffers power supply 1.8 V 1.71 1.8 1.89 V
Related Information
22 The use of Power Management Bus (PMBus*) voltage regulator dedicated to Intel® Agilex™ SmartVID devices is mandatory. The PMBus* voltage regulator and Intel® Agilex™ SmartVID devices are connected via PMBus*.
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message