Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

In single packer per cycle mode, all received TLPs start at the lower 128-bit boundary on a 256-bit Avalon-ST interface. Turn on Enable Multiple Packets per Cycle on the System Settings tab of the parameter editor to change multiple packets per cycle.

Single packer per cycle mode requires simpler Application Layer packet decode logic on the TX and RX paths because packets always start in the lower 128-bits of the Avalon-ST interface. However, the Application Layer must still track Completion Credits to avoid RX buffer overflow. To track Completion Credits, use the following signals to monitor the completion space available and to ensure enough space is available before transmitting Non-Posted requests.

  • ko_cpl_spc_header
  • ko_cpl_spc_data