Quartus® Prime Pro Edition Settings File Reference Manual

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ID 683296
Date 4/11/2025
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Document Table of Contents
Document Table of Contents x
1. Quartus® Prime Pro Edition Settings File Reference Manual
1. Quartus® Prime Pro Edition Settings File Reference Manual x
1.1. Quartus® Prime Pro Edition Settings File Reference Manual Revision History 1.2. Advanced I/O Timing Assignments 1.3. Analysis & Synthesis Assignments 1.4. Assembler Assignments 1.5. Classic Timing Assignments 1.6. Compiler Assignments 1.7. Design Assistant Assignments 1.8. Design Partition Assignments 1.9. EDA Netlist Writer Assignments 1.10. Equivalence Checker Assignments 1.11. Fitter Assignments 1.12. Netlist Viewer Assignments 1.13. Pin & Location Assignments 1.14. Power Estimation Assignments 1.15. Programmer Assignments 1.16. Project-Wide Assignments 1.17. Retimer Assignments 1.18. Retimer Fast Forward Assignments 1.19. Signal Tap Assignments 1.20. Simulator Assignments
1.2. Advanced I/O Timing Assignments x
1.2.1. BOARD_MODEL_EBD_FAR_END 1.2.2. BOARD_MODEL_EBD_FILE_NAME 1.2.3. BOARD_MODEL_EBD_SIGNAL_NAME 1.2.4. BOARD_MODEL_FAR_C 1.2.5. BOARD_MODEL_FAR_DIFFERENTIAL_R 1.2.6. BOARD_MODEL_FAR_PULLDOWN_R 1.2.7. BOARD_MODEL_FAR_PULLUP_R 1.2.8. BOARD_MODEL_FAR_SERIES_R 1.2.9. BOARD_MODEL_NEAR_C 1.2.10. BOARD_MODEL_NEAR_DIFFERENTIAL_R 1.2.11. BOARD_MODEL_NEAR_PULLDOWN_R 1.2.12. BOARD_MODEL_NEAR_PULLUP_R 1.2.13. BOARD_MODEL_NEAR_SERIES_R 1.2.14. BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 1.2.15. BOARD_MODEL_NEAR_TLINE_LENGTH 1.2.16. BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 1.2.17. BOARD_MODEL_TERMINATION_V 1.2.18. BOARD_MODEL_TLINE_C_PER_LENGTH 1.2.19. BOARD_MODEL_TLINE_LENGTH 1.2.20. BOARD_MODEL_TLINE_L_PER_LENGTH 1.2.21. OUTPUT_IO_TIMING_ENDPOINT 1.2.22. OUTPUT_IO_TIMING_FAR_END_VMEAS 1.2.23. OUTPUT_IO_TIMING_NEAR_END_VMEAS
1.3. Analysis & Synthesis Assignments x
1.3.1. ADV_NETLIST_OPT_ALLOWED 1.3.2. ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP 1.3.3. ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION 1.3.4. ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION 1.3.5. ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION 1.3.6. ALLOW_CHILD_PARTITIONS 1.3.7. ALLOW_POWER_UP_DONT_CARE 1.3.8. ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES 1.3.9. ALLOW_SYNCH_CTRL_USAGE 1.3.10. ALTERA_A10_IOPLL_BOOTSTRAP 1.3.11. AUTO_CLOCK_ENABLE_RECOGNITION 1.3.12. AUTO_DSP_RECOGNITION 1.3.13. AUTO_ENABLE_SMART_COMPILE 1.3.14. AUTO_OPEN_DRAIN_PINS 1.3.15. AUTO_PARALLEL_SYNTHESIS 1.3.16. AUTO_RAM_RECOGNITION 1.3.17. AUTO_RESOURCE_SHARING 1.3.18. AUTO_ROM_RECOGNITION 1.3.19. AUTO_SHIFT_REGISTER_RECOGNITION 1.3.20. BLOCK_DESIGN_NAMING 1.3.21. BOARD 1.3.22. DEVICE_FILTER_PACKAGE 1.3.23. DEVICE_FILTER_PIN_COUNT 1.3.24. DEVICE_FILTER_SPEED_GRADE 1.3.25. DEVICE_FILTER_VOLTAGE 1.3.26. DISABLE_DSP_NEGATE_INFERENCING 1.3.27. DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES 1.3.28. DONT_MERGE_REGISTER 1.3.29. DSE_SYNTH_EXTRA_EFFORT_MODE 1.3.30. DSP_BLOCK_BALANCING 1.3.31. EDA_DESIGN_ENTRY_SYNTHESIS_TOOL 1.3.32. EDA_INPUT_DATA_FORMAT 1.3.33. EDA_INPUT_GND_NAME 1.3.34. EDA_INPUT_VCC_NAME 1.3.35. EDA_LMF_FILE 1.3.36. EDA_RUN_TOOL_AUTOMATICALLY 1.3.37. EDA_SHOW_LMF_MAPPING_MESSAGES 1.3.38. EDA_VHDL_LIBRARY 1.3.39. ENABLE_FORMAL_VERIFICATION 1.3.40. ENABLE_STATE_MACHINE_INFERENCE 1.3.41. FAMILY 1.3.42. FORCE_SYNCH_CLEAR 1.3.43. HDL_INITIAL_FANOUT_LIMIT 1.3.44. HDL_MESSAGE_LEVEL 1.3.45. HDL_MESSAGE_OFF 1.3.46. HDL_MESSAGE_ON 1.3.47. HPS_PARTITION 1.3.48. IGNORE_CARRY_BUFFERS 1.3.49. IGNORE_CASCADE_BUFFERS 1.3.50. IGNORE_GLOBAL_BUFFERS 1.3.51. IGNORE_LCELL_BUFFERS 1.3.52. IGNORE_MAX_FANOUT_ASSIGNMENTS 1.3.53. IGNORE_ROW_GLOBAL_BUFFERS 1.3.54. IGNORE_SOFT_BUFFERS 1.3.55. IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF 1.3.56. IMPLEMENT_AS_CLOCK_ENABLE 1.3.57. IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL 1.3.58. INFER_RAMS_FROM_RAW_LOGIC 1.3.59. IP_SEARCH_PATHS 1.3.60. MAX_BALANCING_DSP_BLOCKS 1.3.61. MAX_FANOUT 1.3.62. MAX_LABS 1.3.63. MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 1.3.64. MAX_RAM_BLOCKS_M4K 1.3.65. MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE 1.3.66. MUX_RESTRUCTURE 1.3.67. NOT_GATE_PUSH_BACK 1.3.68. NUMBER_OF_INVERTED_REGISTERS_REPORTED 1.3.69. NUMBER_OF_PROTECTED_REGISTERS_REPORTED 1.3.70. NUMBER_OF_REMOVED_REGISTERS_REPORTED 1.3.71. NUMBER_OF_SWEPT_NODES_REPORTED 1.3.72. OCP_HW_EVAL 1.3.73. OPTIMIZATION_TECHNIQUE 1.3.74. OPTIMIZE_POWER_DURING_SYNTHESIS 1.3.75. PARAMETER 1.3.76. POWER_UP_LEVEL 1.3.77. PRESERVE_FANOUT_FREE_NODE 1.3.78. PRESERVE_REGISTER 1.3.79. PRESERVE_REGISTER_SYN_ONLY 1.3.80. PRPOF_ID 1.3.81. RAMSTYLE_ATTRIBUTE 1.3.82. RBCGEN_CRITICAL_WARNING_TO_ERROR 1.3.83. REMOVE_DUPLICATE_REGISTERS 1.3.84. REMOVE_REDUNDANT_LOGIC_CELLS 1.3.85. REPORT_PARAMETER_SETTINGS_PRO 1.3.86. REPORT_PR_INITIAL_VALUES_AS_ERROR 1.3.87. REPORT_SOURCE_ASSIGNMENTS_PRO 1.3.88. RESYNTHESIS_OPTIMIZATION_EFFORT 1.3.89. RESYNTHESIS_PHYSICAL_SYNTHESIS 1.3.90. RESYNTHESIS_RETIMING 1.3.91. SAFE_STATE_MACHINE 1.3.92. SAVE_DISK_SPACE 1.3.93. SEARCH_PATH 1.3.94. SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL 1.3.95. SIZE_OF_LATCH_REPORT 1.3.96. SIZE_OF_PR_INITIAL_CONDITIONS_REPORT 1.3.97. SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES 1.3.98. STATE_MACHINE_PROCESSING 1.3.99. STRICT_RAM_RECOGNITION 1.3.100. SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 1.3.101. SYNTHESIS_EFFORT 1.3.102. SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER 1.3.103. SYNTHESIS_S10_MIGRATION_CHECKS 1.3.104. SYNTH_CLOCK_MUX_PROTECTION 1.3.105. SYNTH_GATED_CLOCK_CONVERSION 1.3.106. SYNTH_MESSAGE_LEVEL 1.3.107. SYNTH_PROTECT_SDC_CONSTRAINT 1.3.108. SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM 1.3.109. SYNTH_TIMING_DRIVEN_SYNTHESIS 1.3.110. TOP_LEVEL_ENTITY 1.3.111. USER_LIBRARIES 1.3.112. USE_GENERATED_PHYSICAL_CONSTRAINTS 1.3.113. VERILOG_CONSTANT_LOOP_LIMIT 1.3.114. VERILOG_INPUT_VERSION 1.3.115. VERILOG_LMF_FILE 1.3.116. VERILOG_MACRO 1.3.117. VERILOG_NON_CONSTANT_LOOP_LIMIT 1.3.118. VERILOG_SHOW_LMF_MAPPING_MESSAGES 1.3.119. VHDL_INPUT_LIBRARY 1.3.120. VHDL_INPUT_VERSION 1.3.121. VHDL_LMF_FILE 1.3.122. VHDL_SHOW_LMF_MAPPING_MESSAGES
1.4. Assembler Assignments x
1.4.1. AUTO_RESTART_CONFIGURATION 1.4.2. CLOCK_SOURCE 1.4.3. COMPRESSION_MODE 1.4.4. CONFIGURATION_CLOCK_DIVISOR 1.4.5. CONFIGURATION_CLOCK_FREQUENCY 1.4.6. DISABLE_REGISTER_POWERUP_INITIALIZATION 1.4.7. ENABLE_ADV_SEU_DETECTION 1.4.8. ENABLE_AUTONOMOUS_PCIE_HIP 1.4.9. ENABLE_OCT_DONE 1.4.10. EPROM_USE_CHECKSUM_AS_USERCODE 1.4.11. GENERATE_HEX_FILE 1.4.12. GENERATE_PMSF_FILES 1.4.13. GENERATE_PR_RBF_FILE 1.4.14. GENERATE_RBF_FILE 1.4.15. GENERATE_TTF_FILE 1.4.16. HEXOUT_FILE_COUNT_DIRECTION 1.4.17. HEXOUT_FILE_START_ADDRESS 1.4.18. HPS_DAP_SPLIT_MODE 1.4.19. HPS_INITIALIZATION 1.4.20. ON_CHIP_BITSTREAM_DECOMPRESSION 1.4.21. PR_BASE_MSF 1.4.22. PR_BASE_SOF 1.4.23. PR_SKIP_BASE_CHECK 1.4.24. PWRMGT_ADV_CLOCK_DATA_FALL_TIME 1.4.25. PWRMGT_ADV_CLOCK_DATA_RISE_TIME 1.4.26. PWRMGT_ADV_DATA_HOLD_TIME 1.4.27. PWRMGT_ADV_DATA_SETUP_TIME 1.4.28. PWRMGT_ADV_FPGA_RELEASE_DELAY 1.4.29. PWRMGT_ADV_INITIAL_DELAY 1.4.30. PWRMGT_ADV_VOLTAGE_STABLE_DELAY 1.4.31. PWRMGT_ADV_VOUT_READING_ERR_MARGIN 1.4.32. PWRMGT_BUS_SPEED_MODE 1.4.33. PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE 1.4.34. PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 1.4.35. PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 1.4.36. PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 1.4.37. PWRMGT_LINEAR_FORMAT_N 1.4.38. PWRMGT_PAGE_COMMAND_ENABLE 1.4.39. PWRMGT_SLAVE_DEVICE0_ADDRESS 1.4.40. PWRMGT_SLAVE_DEVICE1_ADDRESS 1.4.41. PWRMGT_SLAVE_DEVICE2_ADDRESS 1.4.42. PWRMGT_SLAVE_DEVICE3_ADDRESS 1.4.43. PWRMGT_SLAVE_DEVICE4_ADDRESS 1.4.44. PWRMGT_SLAVE_DEVICE5_ADDRESS 1.4.45. PWRMGT_SLAVE_DEVICE6_ADDRESS 1.4.46. PWRMGT_SLAVE_DEVICE7_ADDRESS 1.4.47. PWRMGT_SLAVE_DEVICE_TYPE 1.4.48. PWRMGT_TABLE_VERSION 1.4.49. PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT 1.4.50. PWRMGT_VOLTAGE_OUTPUT_FORMAT 1.4.51. RELEASE_CLEARS_BEFORE_TRI_STATES 1.4.52. STRATIXII_CONFIGURATION_DEVICE 1.4.53. STRATIX_JTAG_USER_CODE 1.4.54. USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT 1.4.55. USE_CHECKSUM_AS_USERCODE 1.4.56. USE_CONFIGURATION_DEVICE
1.5. Classic Timing Assignments x
1.5.1. ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS 1.5.2. CUT_OFF_IO_PIN_FEEDBACK 1.5.3. CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS 1.5.4. CUT_OFF_READ_DURING_WRITE_PATHS 1.5.5. DEFAULT_HOLD_MULTICYCLE 1.5.6. EMIF_SOC_PHYCLK_ADVANCE_MODELING 1.5.7. ENABLE_HPS_INTERNAL_TIMING 1.5.8. FLOW_ENABLE_TIMING_ANALYZER_AFTER_EARLY_PLACE_STAGE 1.5.9. FLOW_ENABLE_TIMING_ANALYZER_AFTER_PLAN_STAGE 1.5.10. IMPLEMENTS_FREE_RUNNING_CLOCK 1.5.11. INPUT_TRANSITION_TIME 1.5.12. MAX_CORE_JUNCTION_TEMP 1.5.13. MIN_CORE_JUNCTION_TEMP 1.5.14. MIN_MTBF_REQUIREMENT 1.5.15. NOMINAL_CORE_SUPPLY_VOLTAGE 1.5.16. PACKAGE_SKEW_COMPENSATION 1.5.17. PLL_EXTERNAL_FEEDBACK_BOARD_DELAY 1.5.18. TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT 1.5.19. TIMING_ANALYZER_DO_CCPP_REMOVAL 1.5.20. TIMING_ANALYZER_DO_REPORT_TIMING 1.5.21. TIMING_ANALYZER_MULTICORNER_ANALYSIS 1.5.22. TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 1.5.23. TIMING_ANALYZER_REPORT_SCRIPT 1.5.24. TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS 1.5.25. TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS 1.5.26. TIMING_ANALYZER_SIMULTANEOUS_MULTICORNER_ANALYSIS 1.5.27. USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
1.6. Compiler Assignments x
1.6.1. ALLOW_REGISTER_DUPLICATION 1.6.2. ALLOW_REGISTER_MERGING 1.6.3. ALLOW_REGISTER_RETIMING 1.6.4. OPTIMIZATION_MODE
1.7. Design Assistant Assignments x
1.7.1. CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 1.7.2. DA_CUSTOM_RULE_FILE 1.7.3. DRC_DEADLOCK_STATE_LIMIT 1.7.4. DRC_DETAIL_MESSAGE_LIMIT 1.7.5. DRC_FANOUT_EXCEEDING 1.7.6. DRC_GATED_CLOCK_FEED 1.7.7. DRC_REPORT_FANOUT_EXCEEDING 1.7.8. DRC_REPORT_TOP_FANOUT 1.7.9. DRC_TOP_FANOUT 1.7.10. DRC_VIOLATION_MESSAGE_LIMIT 1.7.11. ENABLE_DRC_SETTINGS 1.7.12. HARDCOPY_FLOW_AUTOMATION 1.7.13. HARDCOPY_NEW_PROJECT_PATH 1.7.14. HCPY_CAT 1.7.15. HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES 1.7.16. HCPY_VREF_PINS
1.8. Design Partition Assignments x
1.8.1. ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS 1.8.2. AUTOMATIC_DANGLING_PORT_TIEOFF 1.8.3. CROSS_BOUNDARY_OPTIMIZATIONS 1.8.4. EMPTY 1.8.5. ENABLE_LAB_SHARING_WITH_PARENT_PARTITION 1.8.6. ENABLE_STRICT_PRESERVATION 1.8.7. ENTITY_REBINDING 1.8.8. EXPORT_BLOCK_NAME_OBFUSCATION 1.8.9. IGNORE_PARTITIONS 1.8.10. INCREMENTAL_COMPILATION_EXPORT_FLATTEN 1.8.11. INCREMENTAL_COMPILATION_EXPORT_POST_FIT 1.8.12. INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH 1.8.13. INSERT_BOUNDARY_WIRE_LUTS 1.8.14. MERGE_EQUIVALENT_BIDIRS 1.8.15. MERGE_EQUIVALENT_INPUTS 1.8.16. PARTIAL_RECONFIGURATION_PARTITION 1.8.17. PARTITION 1.8.18. PARTITION_ALWAYS_USE_QXP_NETLIST 1.8.19. PARTITION_ASD_REGION 1.8.20. PARTITION_ASD_REGION_ID 1.8.21. PARTITION_ENABLE_STRICT_PRESERVATION 1.8.22. PARTITION_IGNORE_SOURCE_FILE_CHANGES 1.8.23. PARTITION_PRESERVE_HIGH_SPEED_TILES 1.8.24. PERIPHERY_REUSE_CORE 1.8.25. PRESERVE 1.8.26. PROPAGATE_CONSTANTS_ON_INPUTS 1.8.27. PROPAGATE_INVERSIONS_ON_INPUTS 1.8.28. QDB_FILE_PARTITION 1.8.29. QDB_PATH 1.8.30. REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS
1.9. EDA Netlist Writer Assignments x
1.9.1. EDA_BOARD_BOUNDARY_SCAN_OPERATION 1.9.2. EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL 1.9.3. EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL 1.9.4. EDA_BOARD_DESIGN_SYMBOL_TOOL 1.9.5. EDA_BOARD_DESIGN_TIMING_TOOL 1.9.6. EDA_BOARD_DESIGN_TOOL 1.9.7. EDA_DESIGN_EXTRA_ALTERA_SIM_LIB 1.9.8. EDA_DESIGN_INSTANCE_NAME 1.9.9. EDA_ENABLE_GLITCH_FILTERING 1.9.10. EDA_ENABLE_IPUTF_MODE 1.9.11. EDA_EXTRA_ELAB_OPTION 1.9.12. EDA_FLATTEN_BUSES 1.9.13. EDA_FORMAL_VERIFICATION_ALLOW_RETIMING 1.9.14. EDA_FORMAL_VERIFICATION_TOOL 1.9.15. EDA_FV_HIERARCHY 1.9.16. EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT 1.9.17. EDA_GENERATE_POWER_INPUT_FILE 1.9.18. EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT 1.9.19. EDA_GENERATE_TIMING_CLOSURE_DATA 1.9.20. EDA_IBIS_EXTENDED_MODEL_SELECTOR 1.9.21. EDA_IBIS_MODEL_SELECTOR 1.9.22. EDA_IBIS_MUTUAL_COUPLING 1.9.23. EDA_IBIS_SPECIFICATION_VERSION 1.9.24. EDA_IPFS_FILE 1.9.25. EDA_LAUNCH_CMD_LINE_TOOL 1.9.26. EDA_MAP_ILLEGAL_CHARACTERS 1.9.27. EDA_NATIVELINK_GENERATE_SCRIPT_ONLY 1.9.28. EDA_NATIVELINK_PORTABLE_FILE_PATHS 1.9.29. EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT 1.9.30. EDA_NATIVELINK_SIMULATION_TEST_BENCH 1.9.31. EDA_NETLIST_WRITER_OUTPUT_DIR 1.9.32. EDA_RESYNTHESIS_TOOL 1.9.33. EDA_RTL_SIMULATION_RUN_SCRIPT 1.9.34. EDA_RTL_SIM_MODE 1.9.35. EDA_RTL_TEST_BENCH_FILE_NAME 1.9.36. EDA_RTL_TEST_BENCH_NAME 1.9.37. EDA_RTL_TEST_BENCH_RUN_FOR 1.9.38. EDA_SDC_FILE_NAME 1.9.39. EDA_SIMULATION_RUN_SCRIPT 1.9.40. EDA_SIMULATION_TOOL 1.9.41. EDA_TEST_BENCH_DESIGN_INSTANCE_NAME 1.9.42. EDA_TEST_BENCH_ENABLE_STATUS 1.9.43. EDA_TEST_BENCH_ENTITY_MODULE_NAME 1.9.44. EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB 1.9.45. EDA_TEST_BENCH_FILE 1.9.46. EDA_TEST_BENCH_FILE_NAME 1.9.47. EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY 1.9.48. EDA_TEST_BENCH_MODULE_NAME 1.9.49. EDA_TEST_BENCH_NAME 1.9.50. EDA_TEST_BENCH_RUN_FOR 1.9.51. EDA_TEST_BENCH_RUN_SIM_FOR 1.9.52. EDA_TIME_SCALE 1.9.53. EDA_TIMING_ANALYSIS_TOOL 1.9.54. EDA_TRUNCATE_LONG_HIERARCHY_PATHS 1.9.55. EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY 1.9.56. EDA_VHDL_ARCH_NAME 1.9.57. EDA_WAIT_FOR_GUI_TOOL_COMPLETION 1.9.58. EDA_WRITER_DONT_WRITE_TOP_ENTITY 1.9.59. EDA_WRITE_DEVICE_CONTROL_PORTS 1.9.60. EDA_WRITE_NODES_FOR_POWER_ESTIMATION
1.10. Equivalence Checker Assignments x
1.10.1. EQC_AUTO_BREAK_CONE 1.10.2. EQC_AUTO_COMP_LOOP_CUT 1.10.3. EQC_AUTO_INVERSION 1.10.4. EQC_AUTO_PORTSWAP 1.10.5. EQC_AUTO_TERMINATE 1.10.6. EQC_BBOX_MERGE 1.10.7. EQC_CONSTANT_DFF_DETECTION 1.10.8. EQC_DETECT_DONT_CARES 1.10.9. EQC_DFF_SS_EMULATION 1.10.10. EQC_DUPLICATE_DFF_DETECTION 1.10.11. EQC_LVDS_MERGE 1.10.12. EQC_MAC_REGISTER_UNPACK 1.10.13. EQC_PARAMETER_CHECK 1.10.14. EQC_POWER_UP_COMPARE 1.10.15. EQC_RAM_REGISTER_UNPACK 1.10.16. EQC_RAM_UNMERGING 1.10.17. EQC_RENAMING_RULES 1.10.18. EQC_RENAMING_RULES_LIST 1.10.19. EQC_SET_PARTITION_BB_TO_VCC_GND 1.10.20. EQC_SHOW_ALL_MAPPED_POINTS 1.10.21. EQC_STRUCTURE_MATCHING 1.10.22. EQC_SUB_CONE_REPORT
1.11. Fitter Assignments x
1.11.1. ACTIVE_SERIAL_CLOCK 1.11.2. ALLOW_ROUTING_TO_PERIPHERY_THROUGH_GLOBAL_NETWORK 1.11.3. ALLOW_SEU_FAULT_INJECTION 1.11.4. ALM_REGISTER_PACKING_EFFORT 1.11.5. AUTO_DELAY_CHAINS 1.11.6. AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS 1.11.7. AUTO_GLOBAL_CLOCK 1.11.8. AUTO_GLOBAL_REGISTER_CONTROLS 1.11.9. AUTO_RESERVE_CLKUSR_FOR_CALIBRATION 1.11.10. BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE 1.11.11. BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES 1.11.12. BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS 1.11.13. BLOCK_RAM_TO_MLAB_CELL_CONVERSION 1.11.14. CDR_BANDWIDTH_PRESET 1.11.15. CKN_CK_PAIR 1.11.16. CLOCK_REGION 1.11.17. CONFIGURATION_VCCIO_LEVEL 1.11.18. CONVERT_PR_WARNINGS_TO_ERRORS 1.11.19. CRC_ERROR_OPEN_DRAIN 1.11.20. CURRENT_STRENGTH_NEW 1.11.21. CVP_CONFDONE_OPEN_DRAIN 1.11.22. CVP_MODE 1.11.23. DEVICE 1.11.24. DEVICE_INITIALIZATION_CLOCK 1.11.25. DEVICE_MIGRATION_LIST 1.11.26. DEVICE_TECHNOLOGY_MIGRATION_LIST 1.11.27. DQ_GROUP 1.11.28. DSP_REGISTER_PACKING 1.11.29. DUPLICATE_ATOM 1.11.30. ECO_OPTIMIZE_TIMING 1.11.31. ECO_REGENERATE_REPORT 1.11.32. ENABLE_BUS_HOLD_CIRCUITRY 1.11.33. ENABLE_CRC_ERROR_PIN 1.11.34. ENABLE_CVP_CONFDONE 1.11.35. ENABLE_DEVICE_WIDE_OE 1.11.36. ENABLE_DEVICE_WIDE_RESET 1.11.37. ENABLE_ED_CRC_CHECK 1.11.38. ENABLE_INIT_DONE_OUTPUT 1.11.39. ENABLE_NCEO_OUTPUT 1.11.40. ENABLE_PR_PINS 1.11.41. ENABLE_UNUSED_RX_CLOCK_WORKAROUND 1.11.42. ERROR_CHECK_FREQUENCY_DIVISOR 1.11.43. EXCLUSIVE_IO_GROUP 1.11.44. FINAL_PLACEMENT_OPTIMIZATION 1.11.45. FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION 1.11.46. FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 1.11.47. FITTER_EFFORT 1.11.48. FLEX10K_MAX_PERIPHERAL_OE 1.11.49. FLOW_ENABLE_EARLY_PLACE 1.11.50. FORCE_CONFIGURATION_VCCIO 1.11.51. GLOBAL_SIGNAL 1.11.52. GNDIO_CURRENT_1PT8V 1.11.53. GNDIO_CURRENT_2PT5V 1.11.54. GNDIO_CURRENT_GTL 1.11.55. GNDIO_CURRENT_GTL_PLUS 1.11.56. GNDIO_CURRENT_LVCMOS 1.11.57. GNDIO_CURRENT_LVTTL 1.11.58. GNDIO_CURRENT_PCI 1.11.59. GNDIO_CURRENT_SSTL2_CLASS1 1.11.60. GNDIO_CURRENT_SSTL2_CLASS2 1.11.61. GNDIO_CURRENT_SSTL3_CLASS1 1.11.62. GNDIO_CURRENT_SSTL3_CLASS2 1.11.63. GXB_0PPM_CORECLK 1.11.64. HPS_COLD_RESET_PIN_MODE 1.11.65. HPS_WARM_RESET_PIN_MODE 1.11.66. HSSI_PARAMETER 1.11.67. IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS 1.11.68. INIT_DONE_OPEN_DRAIN 1.11.69. INPUT_DELAY_CHAIN 1.11.70. INPUT_TERMINATION 1.11.71. INTERNAL_SCRUBBING 1.11.72. IO_12_LANE_INPUT_DATA_DELAY_CHAIN 1.11.73. IO_12_LANE_INPUT_STROBE_DELAY_CHAIN 1.11.74. IO_MAXIMUM_TOGGLE_RATE 1.11.75. IO_PARTITION_PLACEMENT 1.11.76. IO_STANDARD 1.11.77. LVDS_DIRECT_LOOPBACK_MODE 1.11.78. MACRO_HEAD 1.11.79. MACRO_MEMBER 1.11.80. MATCH_PLL_COMPENSATION_CLOCK 1.11.81. MIGRATION_DEVICES 1.11.82. MINIMUM_SEU_INTERVAL 1.11.83. MODULE_BLOATING_FACTOR 1.11.84. NCEO_OPEN_DRAIN 1.11.85. NUMBER_OF_EXAMPLE_NODES_REPORTED 1.11.86. OE_DELAY_CHAIN 1.11.87. OPTIMIZE_FOR_METASTABILITY 1.11.88. OPTIMIZE_HOLD_TIMING 1.11.89. OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING 1.11.90. OPTIMIZE_MULTI_CORNER_TIMING 1.11.91. OPTIMIZE_PERSONA_ROUTABILITY 1.11.92. OPTIMIZE_POWER_DURING_FITTING 1.11.93. OPTIMIZE_TIMING 1.11.94. OUTPUT_DELAY_CHAIN 1.11.95. OUTPUT_TERMINATION 1.11.96. PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION 1.11.97. PERIPH_FITTER_SCRIPT 1.11.98. PERIPH_REPORT_SCRIPT 1.11.99. PHYSICAL_SYNTHESIS 1.11.100. PLACEMENT_EFFORT_MULTIPLIER 1.11.101. PLL_AUTO_RESET 1.11.102. PLL_BANDWIDTH_PRESET 1.11.103. PLL_COMPENSATION_MODE 1.11.104. PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING 1.11.105. PRESERVE_UNUSED_XCVR_CHANNEL 1.11.106. PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.11.107. PROGRAMMABLE_POWER_TECHNOLOGY_SETTING 1.11.108. PROGRAMMABLE_PREEMPHASIS 1.11.109. PROGRAMMABLE_VOD 1.11.110. PR_DONE_OPEN_DRAIN 1.11.111. PR_ERROR_OPEN_DRAIN 1.11.112. PR_PINS_OPEN_DRAIN 1.11.113. PR_READY_OPEN_DRAIN 1.11.114. QII_AUTO_PACKED_REGISTERS 1.11.115. RELATIVE_NEUTRON_FLUX 1.11.116. RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP 1.11.117. RESERVE_AVST_CLK_AFTER_CONFIGURATION 1.11.118. RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION 1.11.119. RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION 1.11.120. RESERVE_AVST_VALID_AFTER_CONFIGURATION 1.11.121. RESERVE_DATA0_AFTER_CONFIGURATION 1.11.122. RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION 1.11.123. RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION 1.11.124. RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION 1.11.125. RESERVE_FLEXIBLE_CLOCK_NETWORK 1.11.126. RESERVE_PR_PINS 1.11.127. RESERVE_ROUTING_OUTPUT_FLEXIBILITY 1.11.128. ROUTER_CLOCKING_TOPOLOGY_ANALYSIS 1.11.129. ROUTER_EFFORT_MULTIPLIER 1.11.130. ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION 1.11.131. ROUTER_REGISTER_DUPLICATION 1.11.132. ROUTER_TIMING_OPTIMIZATION_LEVEL 1.11.133. RZQ_GROUP 1.11.134. SDM_DIRECT_TO_FACTORY_IMAGE 1.11.135. SDM_PCIE_CALIB_START 1.11.136. SEED 1.11.137. SEU_FIT_REPORT 1.11.138. SLEW_RATE 1.11.139. SLOW_SLEW_RATE 1.11.140. STRATIXV_CONFIGURATION_SCHEME 1.11.141. STRATIX_DEVICE_IO_STANDARD 1.11.142. SYNCHRONIZER_IDENTIFICATION 1.11.143. SYNCHRONIZER_TOGGLE_RATE 1.11.144. TERMINATION_CONTROL_BLOCK 1.11.145. TREAT_BIDIR_AS_OUTPUT 1.11.146. TRI_STATE_SPI_PINS 1.11.147. UNFORCE_MERGE_PLL 1.11.148. UNUSED_TSD_PINS_GND 1.11.149. USE_AS_3V_GPIO 1.11.150. USE_CONF_DONE 1.11.151. USE_CVP_CONFDONE 1.11.152. USE_HPS_COLD_RESET 1.11.153. USE_HPS_WARM_RESET 1.11.154. USE_INIT_DONE 1.11.155. USE_PWRMGT_ALERT 1.11.156. USE_PWRMGT_PWM0 1.11.157. USE_PWRMGT_SCL 1.11.158. USE_PWRMGT_SDA 1.11.159. USE_SEU_ERROR 1.11.160. USE_UIB_CATTRIP 1.11.161. VCCIO_CURRENT_1PT8V 1.11.162. VCCIO_CURRENT_2PT5V 1.11.163. VCCIO_CURRENT_GTL 1.11.164. VCCIO_CURRENT_GTL_PLUS 1.11.165. VCCIO_CURRENT_LVCMOS 1.11.166. VCCIO_CURRENT_LVTTL 1.11.167. VCCIO_CURRENT_PCI 1.11.168. VCCIO_CURRENT_SSTL2_CLASS1 1.11.169. VCCIO_CURRENT_SSTL2_CLASS2 1.11.170. VCCIO_CURRENT_SSTL3_CLASS1 1.11.171. VCCIO_CURRENT_SSTL3_CLASS2 1.11.172. VID_OPERATION_MODE 1.11.173. VREF_MODE 1.11.174. WEAK_PULL_UP_RESISTOR 1.11.175. XCVR_A10_REFCLK_TERM_TRISTATE 1.11.176. XCVR_A10_RX_ADP_CTLE_ACGAIN_4S 1.11.177. XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL 1.11.178. XCVR_A10_RX_ADP_DFE_FXTAP1 1.11.179. XCVR_A10_RX_ADP_DFE_FXTAP10 1.11.180. XCVR_A10_RX_ADP_DFE_FXTAP10_SGN 1.11.181. XCVR_A10_RX_ADP_DFE_FXTAP11 1.11.182. XCVR_A10_RX_ADP_DFE_FXTAP11_SGN 1.11.183. XCVR_A10_RX_ADP_DFE_FXTAP2 1.11.184. XCVR_A10_RX_ADP_DFE_FXTAP2_SGN 1.11.185. XCVR_A10_RX_ADP_DFE_FXTAP3 1.11.186. XCVR_A10_RX_ADP_DFE_FXTAP3_SGN 1.11.187. XCVR_A10_RX_ADP_DFE_FXTAP4 1.11.188. XCVR_A10_RX_ADP_DFE_FXTAP4_SGN 1.11.189. XCVR_A10_RX_ADP_DFE_FXTAP5 1.11.190. XCVR_A10_RX_ADP_DFE_FXTAP5_SGN 1.11.191. XCVR_A10_RX_ADP_DFE_FXTAP6 1.11.192. XCVR_A10_RX_ADP_DFE_FXTAP6_SGN 1.11.193. XCVR_A10_RX_ADP_DFE_FXTAP7 1.11.194. XCVR_A10_RX_ADP_DFE_FXTAP7_SGN 1.11.195. XCVR_A10_RX_ADP_DFE_FXTAP8 1.11.196. XCVR_A10_RX_ADP_DFE_FXTAP8_SGN 1.11.197. XCVR_A10_RX_ADP_DFE_FXTAP9 1.11.198. XCVR_A10_RX_ADP_DFE_FXTAP9_SGN 1.11.199. XCVR_A10_RX_ADP_VGA_SEL 1.11.200. XCVR_A10_RX_EQ_BW_SEL 1.11.201. XCVR_A10_RX_EQ_DC_GAIN_TRIM 1.11.202. XCVR_A10_RX_LINK 1.11.203. XCVR_A10_RX_ONE_STAGE_ENABLE 1.11.204. XCVR_A10_RX_TERM_SEL 1.11.205. XCVR_A10_TX_COMPENSATION_EN 1.11.206. XCVR_A10_TX_LINK 1.11.207. XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP 1.11.208. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP 1.11.209. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T 1.11.210. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T 1.11.211. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 1.11.212. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP 1.11.213. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 1.11.214. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T 1.11.215. XCVR_A10_TX_SLEW_RATE_CTRL 1.11.216. XCVR_A10_TX_TERM_SEL 1.11.217. XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 1.11.218. XCVR_A10_TX_XTX_PATH_ANALOG_MODE 1.11.219. XCVR_C10_REFCLK_TERM_TRISTATE 1.11.220. XCVR_C10_RX_ADP_CTLE_ACGAIN_4S 1.11.221. XCVR_C10_RX_ADP_CTLE_EQZ_1S_SEL 1.11.222. XCVR_C10_RX_ADP_DFE_FXTAP1 1.11.223. XCVR_C10_RX_ADP_DFE_FXTAP10 1.11.224. XCVR_C10_RX_ADP_DFE_FXTAP10_SGN 1.11.225. XCVR_C10_RX_ADP_DFE_FXTAP11 1.11.226. XCVR_C10_RX_ADP_DFE_FXTAP11_SGN 1.11.227. XCVR_C10_RX_ADP_DFE_FXTAP2 1.11.228. XCVR_C10_RX_ADP_DFE_FXTAP2_SGN 1.11.229. XCVR_C10_RX_ADP_DFE_FXTAP3 1.11.230. XCVR_C10_RX_ADP_DFE_FXTAP3_SGN 1.11.231. XCVR_C10_RX_ADP_DFE_FXTAP4 1.11.232. XCVR_C10_RX_ADP_DFE_FXTAP4_SGN 1.11.233. XCVR_C10_RX_ADP_DFE_FXTAP5 1.11.234. XCVR_C10_RX_ADP_DFE_FXTAP5_SGN 1.11.235. XCVR_C10_RX_ADP_DFE_FXTAP6 1.11.236. XCVR_C10_RX_ADP_DFE_FXTAP6_SGN 1.11.237. XCVR_C10_RX_ADP_DFE_FXTAP7 1.11.238. XCVR_C10_RX_ADP_DFE_FXTAP7_SGN 1.11.239. XCVR_C10_RX_ADP_DFE_FXTAP8 1.11.240. XCVR_C10_RX_ADP_DFE_FXTAP8_SGN 1.11.241. XCVR_C10_RX_ADP_DFE_FXTAP9 1.11.242. XCVR_C10_RX_ADP_DFE_FXTAP9_SGN 1.11.243. XCVR_C10_RX_ADP_VGA_SEL 1.11.244. XCVR_C10_RX_EQ_BW_SEL 1.11.245. XCVR_C10_RX_EQ_DC_GAIN_TRIM 1.11.246. XCVR_C10_RX_LINK 1.11.247. XCVR_C10_RX_ONE_STAGE_ENABLE 1.11.248. XCVR_C10_RX_TERM_SEL 1.11.249. XCVR_C10_TX_COMPENSATION_EN 1.11.250. XCVR_C10_TX_LINK 1.11.251. XCVR_C10_TX_PRE_EMP_SIGN_1ST_POST_TAP 1.11.252. XCVR_C10_TX_PRE_EMP_SIGN_2ND_POST_TAP 1.11.253. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_1T 1.11.254. XCVR_C10_TX_PRE_EMP_SIGN_PRE_TAP_2T 1.11.255. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 1.11.256. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP 1.11.257. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 1.11.258. XCVR_C10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T 1.11.259. XCVR_C10_TX_SLEW_RATE_CTRL 1.11.260. XCVR_C10_TX_TERM_SEL 1.11.261. XCVR_C10_TX_VOD_OUTPUT_SWING_CTRL 1.11.262. XCVR_C10_TX_XTX_PATH_ANALOG_MODE 1.11.263. XCVR_RECONFIG_GROUP 1.11.264. XCVR_S10_REFCLK_TERM_TRISTATE 1.11.265. XCVR_USE_HQ_REFCLK 1.11.266. XCVR_USE_SKEW_BALANCED 1.11.267. XCVR_VCCR_VCCT_VOLTAGE
1.12. Netlist Viewer Assignments x
1.12.1. RTLV_GROUP_COMB_LOGIC_IN_CLOUD 1.12.2. RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV 1.12.3. RTLV_GROUP_RELATED_NODES 1.12.4. RTLV_GROUP_RELATED_NODES_TMV 1.12.5. RTLV_REMOVE_FANOUT_FREE_REGISTERS 1.12.6. RTLV_SIMPLIFIED_LOGIC
1.13. Pin & Location Assignments x
1.13.1. FAST_INPUT_REGISTER 1.13.2. FAST_OUTPUT_ENABLE_REGISTER 1.13.3. FAST_OUTPUT_REGISTER 1.13.4. IP_DEBUG_VISIBLE 1.13.5. LOCATION 1.13.6. PIN_CONNECT_FROM_NODE 1.13.7. RESERVE_PIN 1.13.8. SUBCLIQUE_OF 1.13.9. VIRTUAL_PIN
1.14. Power Estimation Assignments x
1.14.1. ENABLE_SMART_VOLTAGE_ID 1.14.2. POWER_APPLY_THERMAL_MARGIN 1.14.3. POWER_AUTO_COMPUTE_TJ 1.14.4. POWER_BOARD_TEMPERATURE 1.14.5. POWER_BOARD_THERMAL_MODEL 1.14.6. POWER_COOLING_FOR_MAX_TJ 1.14.7. POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 1.14.8. POWER_DEFAULT_TOGGLE_RATE 1.14.9. POWER_GLITCH_FACTOR 1.14.10. POWER_HPS_DYNAMIC_POWER_DUAL 1.14.11. POWER_HPS_DYNAMIC_POWER_SINGLE 1.14.12. POWER_HPS_ENABLE 1.14.13. POWER_HPS_JUNCTION_TEMPERATURE 1.14.14. POWER_HPS_PROC_FREQ 1.14.15. POWER_HPS_STATIC_POWER 1.14.16. POWER_HPS_TOTAL_POWER 1.14.17. POWER_HSSI 1.14.18. POWER_HSSI_LEFT 1.14.19. POWER_HSSI_RIGHT 1.14.20. POWER_HSSI_VCCHIP_LEFT 1.14.21. POWER_HSSI_VCCHIP_RIGHT 1.14.22. POWER_INPUT_FILE_NAME 1.14.23. POWER_INPUT_FILE_TYPE 1.14.24. POWER_MAX_TJ_VALUE 1.14.25. POWER_OCS_VALUE 1.14.26. POWER_OJB_VALUE 1.14.27. POWER_OJC_VALUE 1.14.28. POWER_OSA_VALUE 1.14.29. POWER_OUTPUT_SAF_NAME 1.14.30. POWER_PRESET_COOLING_SOLUTION 1.14.31. POWER_READ_INPUT_FILE 1.14.32. POWER_REPORT_POWER_DISSIPATION 1.14.33. POWER_REPORT_SIGNAL_ACTIVITY 1.14.34. POWER_STATIC_PROBABILITY 1.14.35. POWER_TJ_VALUE 1.14.36. POWER_TOGGLE_RATE 1.14.37. POWER_TOGGLE_RATE_PERCENTAGE 1.14.38. POWER_USE_CUSTOM_COOLING_SOLUTION 1.14.39. POWER_USE_DEVICE_CHARACTERISTICS 1.14.40. POWER_USE_INPUT_FILES 1.14.41. POWER_USE_PVA 1.14.42. POWER_USE_TA_VALUE 1.14.43. POWER_VCCAUX_USER_OPTION 1.14.44. POWER_VCCA_GXBL_USER_OPTION 1.14.45. POWER_VCCA_GXBR_USER_OPTION 1.14.46. POWER_VCCA_GXB_USER_OPTION 1.14.47. POWER_VCCA_L_USER_OPTION 1.14.48. POWER_VCCA_R_USER_OPTION 1.14.49. POWER_VCCCB_USER_OPTION 1.14.50. POWER_VCCH_GXBL_USER_OPTION 1.14.51. POWER_VCCH_GXBR_USER_OPTION 1.14.52. POWER_VCCH_GXB_USER_OPTION 1.14.53. POWER_VCCIO_USER_OPTION 1.14.54. POWER_VCCL_GXB_USER_OPTION 1.14.55. POWER_VCCPD_USER_OPTION 1.14.56. POWER_VCCR_GXBL_USER_OPTION 1.14.57. POWER_VCCR_GXBR_USER_OPTION 1.14.58. POWER_VCCR_GXB_USER_OPTION 1.14.59. POWER_VCCT_GXBL_USER_OPTION 1.14.60. POWER_VCCT_GXBR_USER_OPTION 1.14.61. POWER_VCCT_GXB_USER_OPTION 1.14.62. POWER_VCD_FILE_END_TIME 1.14.63. POWER_VCD_FILE_START_TIME 1.14.64. POWER_VCD_FILTER_GLITCHES 1.14.65. VCCAUX_SHARED_USER_VOLTAGE 1.14.66. VCCAUX_USER_VOLTAGE 1.14.67. VCCA_FPLL_USER_VOLTAGE 1.14.68. VCCA_GTBR_USER_VOLTAGE 1.14.69. VCCA_GTB_USER_VOLTAGE 1.14.70. VCCA_GXBL_USER_VOLTAGE 1.14.71. VCCA_GXBR_USER_VOLTAGE 1.14.72. VCCA_GXB_USER_VOLTAGE 1.14.73. VCCA_L_USER_VOLTAGE 1.14.74. VCCA_PLL_USER_VOLTAGE 1.14.75. VCCA_R_USER_VOLTAGE 1.14.76. VCCA_USER_VOLTAGE 1.14.77. VCCBAT_USER_VOLTAGE 1.14.78. VCCCB_USER_VOLTAGE 1.14.79. VCCD_FPLL_USER_VOLTAGE 1.14.80. VCCD_PLL_USER_VOLTAGE 1.14.81. VCCD_USER_VOLTAGE 1.14.82. VCCEH_GXBL_USER_VOLTAGE 1.14.83. VCCEH_GXBR_USER_VOLTAGE 1.14.84. VCCEH_GXB_USER_VOLTAGE 1.14.85. VCCERAM_USER_VOLTAGE 1.14.86. VCCE_GXBL_USER_VOLTAGE 1.14.87. VCCE_GXBR_USER_VOLTAGE 1.14.88. VCCE_GXB_USER_VOLTAGE 1.14.89. VCCE_USER_VOLTAGE 1.14.90. VCCHIP_L_USER_VOLTAGE 1.14.91. VCCHIP_R_USER_VOLTAGE 1.14.92. VCCHIP_USER_VOLTAGE 1.14.93. VCCHSSI_L_USER_VOLTAGE 1.14.94. VCCHSSI_R_USER_VOLTAGE 1.14.95. VCCH_GTBR_USER_VOLTAGE 1.14.96. VCCH_GTB_USER_VOLTAGE 1.14.97. VCCH_GXBL_USER_VOLTAGE 1.14.98. VCCH_GXBR_USER_VOLTAGE 1.14.99. VCCH_GXB_USER_VOLTAGE 1.14.100. VCCH_L_USER_VOLTAGE 1.14.101. VCCH_R_USER_VOLTAGE 1.14.102. VCCINT_USER_VOLTAGE 1.14.103. VCCIOREF_HPS_USER_VOLTAGE 1.14.104. VCCIO_HPS_USER_VOLTAGE 1.14.105. VCCIO_USER_VOLTAGE 1.14.106. VCCL_GTBL_USER_VOLTAGE 1.14.107. VCCL_GTBR_USER_VOLTAGE 1.14.108. VCCL_GTB_USER_VOLTAGE 1.14.109. VCCL_GXBL_USER_VOLTAGE 1.14.110. VCCL_GXBR_USER_VOLTAGE 1.14.111. VCCL_GXB_USER_VOLTAGE 1.14.112. VCCL_HPS_USER_VOLTAGE 1.14.113. VCCL_USER_VOLTAGE 1.14.114. VCCPD_USER_VOLTAGE 1.14.115. VCCPGM_USER_VOLTAGE 1.14.116. VCCPLL_HPS_USER_VOLTAGE 1.14.117. VCCPT_USER_VOLTAGE 1.14.118. VCCP_USER_VOLTAGE 1.14.119. VCCRSTCLK_HPS_USER_VOLTAGE 1.14.120. VCCR_GTBL_USER_VOLTAGE 1.14.121. VCCR_GTBR_USER_VOLTAGE 1.14.122. VCCR_GTB_USER_VOLTAGE 1.14.123. VCCR_GXBL_USER_VOLTAGE 1.14.124. VCCR_GXBR_USER_VOLTAGE 1.14.125. VCCR_GXB_USER_VOLTAGE 1.14.126. VCCR_L_USER_VOLTAGE 1.14.127. VCCR_R_USER_VOLTAGE 1.14.128. VCCR_USER_VOLTAGE 1.14.129. VCCT_GTBL_USER_VOLTAGE 1.14.130. VCCT_GTBR_USER_VOLTAGE 1.14.131. VCCT_GTB_USER_VOLTAGE 1.14.132. VCCT_GXBL_USER_VOLTAGE 1.14.133. VCCT_GXBR_USER_VOLTAGE 1.14.134. VCCT_GXB_USER_VOLTAGE 1.14.135. VCCT_L_USER_VOLTAGE 1.14.136. VCCT_R_USER_VOLTAGE 1.14.137. VCCT_USER_VOLTAGE 1.14.138. VCC_HPS_USER_VOLTAGE 1.14.139. VCC_USER_VOLTAGE
1.15. Programmer Assignments x
1.15.1. GENERATE_CONFIG_HEXOUT_FILE 1.15.2. GENERATE_CONFIG_ISC_FILE 1.15.3. GENERATE_CONFIG_JAM_FILE 1.15.4. GENERATE_CONFIG_JBC_FILE 1.15.5. GENERATE_CONFIG_JBC_FILE_COMPRESSED 1.15.6. GENERATE_CONFIG_SVF_FILE 1.15.7. GENERATE_JAM_FILE 1.15.8. GENERATE_JBC_FILE 1.15.9. GENERATE_JBC_FILE_COMPRESSED 1.15.10. GENERATE_SVF_FILE 1.15.11. HPS_EARLY_IO_RELEASE 1.15.12. MERGE_HEX_FILE
1.16. Project-Wide Assignments x
1.16.1. AGGREGATE_REVISION 1.16.2. AHDL_FILE 1.16.3. AHDL_TEXT_DESIGN_OUTPUT_FILE 1.16.4. ALLOW_DSP_RETIMING 1.16.5. ALLOW_RAM_RETIMING 1.16.6. ASM_FILE 1.16.7. AUTO_EXPORT_VER_COMPATIBLE_DB 1.16.8. BASE_REVISION_PROJECT_OUTPUT_DIRECTORY 1.16.9. BDF_FILE 1.16.10. BINARY_FILE 1.16.11. BSF_FILE 1.16.12. CDF_FILE 1.16.13. COMMAND_MACRO_FILE 1.16.14. CPP_FILE 1.16.15. CPP_INCLUDE_FILE 1.16.16. CUSP_FILE 1.16.17. CVP_REVISION 1.16.18. C_FILE 1.16.19. DEPENDENCY_FILE 1.16.20. DSPBUILDER_FILE 1.16.21. EDIF_FILE 1.16.22. ELF_FILE 1.16.23. ENABLE_COMPACT_REPORT_TABLE 1.16.24. ENABLE_REDUCED_MEMORY_MODE 1.16.25. EQUATION_FILE 1.16.26. FLOW_DISABLE_ASSEMBLER 1.16.27. FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS 1.16.28. FLOW_ENABLE_PARALLEL_MODULES 1.16.29. FLOW_ENABLE_POWER_ANALYZER 1.16.30. FLOW_ENABLE_RTL_VIEWER 1.16.31. GDF_FILE 1.16.32. HEX_FILE 1.16.33. HEX_OUTPUT_FILE 1.16.34. HPS_ISW_DATA 1.16.35. HPS_ISW_EMIF 1.16.36. HPS_ISW_FILE 1.16.37. HTML_FILE 1.16.38. HTML_REPORT_FILE 1.16.39. INCLUDE_FILE 1.16.40. INVALID_DESIGN_SOURCE 1.16.41. IPX_FILE 1.16.42. IP_COMPONENT_AUTHOR 1.16.43. IP_COMPONENT_DESCRIPTION 1.16.44. IP_COMPONENT_DISPLAY_NAME 1.16.45. IP_COMPONENT_DOCUMENTATION_LINK 1.16.46. IP_COMPONENT_GROUP 1.16.47. IP_COMPONENT_INTERNAL 1.16.48. IP_COMPONENT_NAME 1.16.49. IP_COMPONENT_PARAMETER 1.16.50. IP_COMPONENT_REPORT_HIERARCHY 1.16.51. IP_COMPONENT_VERSION 1.16.52. IP_FILE 1.16.53. IP_GENERATED_DEVICE_FAMILY 1.16.54. IP_QSYS_MODE 1.16.55. IP_TARGETED_DEVICE_FAMILY 1.16.56. IP_TARGETED_PART_TRAIT 1.16.57. IP_TOOL_ENV 1.16.58. IP_TOOL_HIERARCHY_LEVELS 1.16.59. IP_TOOL_NAME 1.16.60. IP_TOOL_VENDOR_NAME 1.16.61. IP_TOOL_VERSION 1.16.62. IP_TOOL_VERSION_CREATED 1.16.63. IP_TOP_LEVEL_COMPONENT_NAME 1.16.64. IP_TOP_LEVEL_ENTITY_NAME 1.16.65. JAM_FILE 1.16.66. JBC_FILE 1.16.67. LICENSE_FILE 1.16.68. LMF_FILE 1.16.69. LOGIC_ANALYZER_INTERFACE_FILE 1.16.70. MAP_FILE 1.16.71. MASK_REVISION 1.16.72. MAX_IGNORED_ASGN_MSG 1.16.73. MESSAGE_DISABLE 1.16.74. MESSAGE_ENABLE 1.16.75. MIF_FILE 1.16.76. MISC_FILE 1.16.77. NUM_PARALLEL_PROCESSORS 1.16.78. OBJECT_FILE 1.16.79. OCP_FILE 1.16.80. PARTIAL_SRAM_OBJECT_FILE 1.16.81. PIN_FILE 1.16.82. POWER_INPUT_FILE 1.16.83. PPF_FILE 1.16.84. PROGRAMMER_OBJECT_FILE 1.16.85. PROJECT_OUTPUT_DIRECTORY 1.16.86. PROJECT_USE_SIMPLIFIED_NAMES 1.16.87. QARLOG_FILE 1.16.88. QAR_FILE 1.16.89. QIP_FILE 1.16.90. QSYS_FILE 1.16.91. QUARTUS_PTF_FILE 1.16.92. QUARTUS_SBD_FILE 1.16.93. QUARTUS_STANDARD_DELAY_FILE 1.16.94. RAW_BINARY_FILE 1.16.95. READ_OR_WRITE_IN_BYTE_ADDRESS 1.16.96. RECONFIGURABLE_REVISION 1.16.97. REVISION_TYPE 1.16.98. RUN_FULL_COMPILE_ON_DEVICE_CHANGE 1.16.99. SBI_FILE 1.16.100. SDC_ENTITY_FILE 1.16.101. SDC_ENTITY_HELPER_FILE 1.16.102. SDC_FILE 1.16.103. SDF_OUTPUT_FILE 1.16.104. SERIAL_BITSTREAM_FILE 1.16.105. SIGNALTAP_FILE 1.16.106. SIP_FILE 1.16.107. SLD_FILE 1.16.108. SMF_FILE 1.16.109. SOFTWARE_LIBRARY_FILE 1.16.110. SOPCINFO_FILE 1.16.111. SOPC_FILE 1.16.112. SOURCE_TCL_SCRIPT_FILE 1.16.113. SPD_FILE 1.16.114. SRAM_OBJECT_FILE 1.16.115. SRECORDS_FILE 1.16.116. SVF_FILE 1.16.117. SYM_FILE 1.16.118. SYNTHESIS_ONLY_QIP 1.16.119. SYSTEMVERILOG_FILE 1.16.120. TCL_ENTITY_FILE 1.16.121. TCL_SCRIPT_FILE 1.16.122. TEMPLATE_FILE 1.16.123. TEXT_FILE 1.16.124. TEXT_FORMAT_REPORT_FILE 1.16.125. TIMING_ANALYSIS_OUTPUT_FILE 1.16.126. VCD_FILE 1.16.127. VECTOR_TABLE_OUTPUT_FILE 1.16.128. VECTOR_TEXT_FILE 1.16.129. VECTOR_WAVEFORM_FILE 1.16.130. VERILOG_FILE 1.16.131. VERILOG_INCLUDE_FILE 1.16.132. VERILOG_OUTPUT_FILE 1.16.133. VERILOG_TEST_BENCH_FILE 1.16.134. VER_COMPATIBLE_DB_DIR 1.16.135. VHDL_FILE 1.16.136. VHDL_OUTPUT_FILE 1.16.137. VHDL_TEST_BENCH_FILE 1.16.138. VQM_FILE 1.16.139. ZIP_VECTOR_WAVEFORM_FILE
1.17. Retimer Assignments x
1.17.1. HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX 1.17.2. HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR 1.17.3. HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS 1.17.4. HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS 1.17.5. HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION
1.18. Retimer Fast Forward Assignments x
1.18.1. CRITICAL_CHAIN_VIEWER 1.18.2. FLOW_ENABLE_HYPER_RETIMER_FAST_FORWARD
1.19. Signal Tap Assignments x
1.19.1. CREATE_PARTITION_BOUNDARY_PORTS 1.19.2. ENABLE_LOGIC_ANALYZER_INTERFACE 1.19.3. ENABLE_SIGNALTAP 1.19.4. STP_FILE 1.19.5. USE_LOGIC_ANALYZER_INTERFACE_FILE 1.19.6. USE_SIGNALTAP_FILE
1.20. Simulator Assignments x
1.20.1. ACTION 1.20.2. ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS 1.20.3. ADD_TO_SIMULATION_OUTPUT_WAVEFORMS 1.20.4. ALIAS 1.20.5. AUTO_USE_SIMULATION_PDB_NETLIST 1.20.6. BREAKPOINT_STATE 1.20.7. CHECK_OUTPUTS 1.20.8. END_TIME 1.20.9. EXTERNAL_PIN_CONNECTION 1.20.10. GLITCH_DETECTION 1.20.11. GLITCH_INTERVAL 1.20.12. IMMEDIATE_ASSERTION_FAIL_ACTION 1.20.13. IMMEDIATE_ASSERTION_FAIL_MESSAGE 1.20.14. IMMEDIATE_ASSERTION_PASS_MESSAGE 1.20.15. IMMEDIATE_ASSERTION_STATE 1.20.16. IMMEDIATE_ASSERTION_TEST_CONDITION 1.20.17. INCREMENTAL_VECTOR_INPUT_SOURCE 1.20.18. PASSIVE_RESISTOR 1.20.19. SETUP_HOLD_DETECTION 1.20.20. SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED 1.20.21. SETUP_HOLD_TIME_VIOLATION_DETECTION 1.20.22. SIMULATION_BUS_CHANNEL_GROUPING 1.20.23. SIMULATION_COMPARE_SIGNAL 1.20.24. SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL 1.20.25. SIMULATION_COVERAGE 1.20.26. SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE 1.20.27. SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL 1.20.28. SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL 1.20.29. SIMULATION_MODE 1.20.30. SIMULATION_NETLIST_VIEWER 1.20.31. SIMULATION_SIGNAL_COMPARE_TOLERANCE 1.20.32. SIMULATION_VDB_RESULT_FLUSH 1.20.33. SIMULATION_VECTOR_COMPARE_BEGIN_TIME 1.20.34. SIMULATION_VECTOR_COMPARE_END_TIME 1.20.35. SIMULATION_VECTOR_COMPARE_RULE_FOR_0 1.20.36. SIMULATION_VECTOR_COMPARE_RULE_FOR_1 1.20.37. SIMULATION_VECTOR_COMPARE_RULE_FOR_DC 1.20.38. SIMULATION_VECTOR_COMPARE_RULE_FOR_H 1.20.39. SIMULATION_VECTOR_COMPARE_RULE_FOR_L 1.20.40. SIMULATION_VECTOR_COMPARE_RULE_FOR_U 1.20.41. SIMULATION_VECTOR_COMPARE_RULE_FOR_W 1.20.42. SIMULATION_VECTOR_COMPARE_RULE_FOR_X 1.20.43. SIMULATION_VECTOR_COMPARE_RULE_FOR_Z 1.20.44. SIM_BEHAVIOR_SIMULATION 1.20.45. SIM_COMPILE_HDL_FILES 1.20.46. SIM_HDL_TOP_MODULE_NAME 1.20.47. SIM_OVERWRITE_WAVEFORM_INPUTS 1.20.48. SIM_TAP_REGISTER_D_Q_PORTS 1.20.49. SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 1.20.50. SIM_VECTOR_COMPARED_CLOCK_OFFSET 1.20.51. SIM_VECTOR_COMPARED_CLOCK_PERIOD 1.20.52. START_TIME 1.20.53. TRIGGER_EQUATION 1.20.54. TRIGGER_VECTOR_COMPARE_ON_SIGNAL 1.20.55. USER_MESSAGE 1.20.56. VECTOR_COMPARE_TRIGGER_MODE 1.20.57. VECTOR_INPUT_SOURCE 1.20.58. VECTOR_OUTPUT_DESTINATION 1.20.59. VECTOR_OUTPUT_FORMAT 1.20.60. X_ON_VIOLATION_OPTION
1. Quartus® Prime Pro Edition Settings File Reference Manual

Power Estimation Assignments


Section Content
EARLY_POWER_ESTIMATOR_EXPORT_FILE
ENABLE_SMART_VOLTAGE_ID
POWER_ADDITIONAL_MARGIN_PERCENTAGE
POWER_AND_THERMAL_CALCULATOR_EXPORT_FILE
POWER_APPLY_THERMAL_MARGIN
POWER_AUTO_COMPUTE_TJ
POWER_BOARD_TEMPERATURE
POWER_BOARD_THERMAL_MODEL
POWER_COOLING_FOR_MAX_TJ
POWER_DEFAULT_INPUT_IO_TOGGLE_RATE
POWER_DEFAULT_TOGGLE_RATE
POWER_GLITCH_FACTOR
POWER_HPS_DYNAMIC_POWER_DUAL
POWER_HPS_DYNAMIC_POWER_SINGLE
POWER_HPS_ENABLE
POWER_HPS_JUNCTION_TEMPERATURE
POWER_HPS_PROC_FREQ
POWER_HPS_STATIC_POWER
POWER_HPS_TOTAL_POWER
POWER_HSSI
POWER_HSSI_LEFT
POWER_HSSI_RIGHT
POWER_HSSI_VCCHIP_LEFT
POWER_HSSI_VCCHIP_RIGHT
POWER_INPUT_FILE_NAME
POWER_INPUT_FILE_TYPE
POWER_MAX_TJ_VALUE
POWER_OCS_VALUE
POWER_OJB_VALUE
POWER_OJC_VALUE
POWER_OSA_VALUE
POWER_OUTPUT_SAF_NAME
POWER_PRESET_COOLING_SOLUTION
POWER_PSI_CA_VALUE
POWER_READ_INPUT_FILE
POWER_REPORT_POWER_DISSIPATION
POWER_REPORT_SIGNAL_ACTIVITY
POWER_STATIC_PROBABILITY
POWER_TEMPERATURE_MEASUREMENT_METHOD
POWER_THERMAL_SOLVER_MODE
POWER_TJ_VALUE
POWER_TOGGLE_RATE
POWER_TOGGLE_RATE_PERCENTAGE
POWER_USER_LIFE_VALUE
POWER_USE_CUSTOM_COOLING_SOLUTION
POWER_USE_DEVICE_CHARACTERISTICS
POWER_USE_INPUT_FILES
POWER_USE_PVA
POWER_USE_TA_VALUE
POWER_VCCAUX_USER_OPTION
POWER_VCCA_GXBL_USER_OPTION
POWER_VCCA_GXBR_USER_OPTION
POWER_VCCA_GXB_USER_OPTION
POWER_VCCA_L_USER_OPTION
POWER_VCCA_R_USER_OPTION
POWER_VCCCB_USER_OPTION
POWER_VCCH_GXBL_USER_OPTION
POWER_VCCH_GXBR_USER_OPTION
POWER_VCCH_GXB_USER_OPTION
POWER_VCCIO_USER_OPTION
POWER_VCCL_GXB_USER_OPTION
POWER_VCCPD_USER_OPTION
POWER_VCCR_GXBL_USER_OPTION
POWER_VCCR_GXBR_USER_OPTION
POWER_VCCR_GXB_USER_OPTION
POWER_VCCT_GXBL_USER_OPTION
POWER_VCCT_GXBR_USER_OPTION
POWER_VCCT_GXB_USER_OPTION
POWER_VCD_FILE_END_TIME
POWER_VCD_FILE_START_TIME
POWER_VCD_FILTER_GLITCHES
VCCAUX_SHARED_USER_VOLTAGE
VCCAUX_USER_VOLTAGE
VCCA_FPLL_USER_VOLTAGE
VCCA_GTBR_USER_VOLTAGE
VCCA_GTB_USER_VOLTAGE
VCCA_GXBL_USER_VOLTAGE
VCCA_GXBR_USER_VOLTAGE
VCCA_GXB_USER_VOLTAGE
VCCA_L_USER_VOLTAGE
VCCA_PLL_USER_VOLTAGE
VCCA_R_USER_VOLTAGE
VCCA_USER_VOLTAGE
VCCBAT_USER_VOLTAGE
VCCCB_USER_VOLTAGE
VCCD_FPLL_USER_VOLTAGE
VCCD_PLL_USER_VOLTAGE
VCCD_USER_VOLTAGE
VCCEH_GXBL_USER_VOLTAGE
VCCEH_GXBR_USER_VOLTAGE
VCCEH_GXB_USER_VOLTAGE
VCCERAM_USER_VOLTAGE
VCCE_GXBL_USER_VOLTAGE
VCCE_GXBR_USER_VOLTAGE
VCCE_GXB_USER_VOLTAGE
VCCE_USER_VOLTAGE
VCCHIP_L_USER_VOLTAGE
VCCHIP_R_USER_VOLTAGE
VCCHIP_USER_VOLTAGE
VCCHSSI_L_USER_VOLTAGE
VCCHSSI_R_USER_VOLTAGE
VCCH_GTBR_USER_VOLTAGE
VCCH_GTB_USER_VOLTAGE
VCCH_GXBL_USER_VOLTAGE
VCCH_GXBR_USER_VOLTAGE
VCCH_GXB_USER_VOLTAGE
VCCH_L_USER_VOLTAGE
VCCH_R_USER_VOLTAGE
VCCINT_USER_VOLTAGE
VCCIOREF_HPS_USER_VOLTAGE
VCCIO_HPS_USER_VOLTAGE
VCCIO_USER_VOLTAGE
VCCL_GTBL_USER_VOLTAGE
VCCL_GTBR_USER_VOLTAGE
VCCL_GTB_USER_VOLTAGE
VCCL_GXBL_USER_VOLTAGE
VCCL_GXBR_USER_VOLTAGE
VCCL_GXB_USER_VOLTAGE
VCCL_HPS_USER_VOLTAGE
VCCL_USER_VOLTAGE
VCCPD_USER_VOLTAGE
VCCPGM_USER_VOLTAGE
VCCPLL_HPS_USER_VOLTAGE
VCCPT_USER_VOLTAGE
VCCP_USER_VOLTAGE
VCCRSTCLK_HPS_USER_VOLTAGE
VCCR_GTBL_USER_VOLTAGE
VCCR_GTBR_USER_VOLTAGE
VCCR_GTB_USER_VOLTAGE
VCCR_GXBL_USER_VOLTAGE
VCCR_GXBR_USER_VOLTAGE
VCCR_GXB_USER_VOLTAGE
VCCR_L_USER_VOLTAGE
VCCR_R_USER_VOLTAGE
VCCR_USER_VOLTAGE
VCCT_GTBL_USER_VOLTAGE
VCCT_GTBR_USER_VOLTAGE
VCCT_GTB_USER_VOLTAGE
VCCT_GXBL_USER_VOLTAGE
VCCT_GXBR_USER_VOLTAGE
VCCT_GXB_USER_VOLTAGE
VCCT_L_USER_VOLTAGE
VCCT_R_USER_VOLTAGE
VCCT_USER_VOLTAGE
VCC_HPS_USER_VOLTAGE
VCC_USER_VOLTAGE

Level Two Title