Agilex™ 7 FPGA I-Series Development Kit User Guide

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ID 683288
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide A. Development Kits Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Box Contents 1.3. Operating Conditions
2. Getting Started x
2.1. About Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. About Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch Settings 3.3. How to Generate a POF Image to Program the Flash 3.4. How to Program the Generated POF Image 3.5. The Required SmartVID QSF Assignments to Compile a Design
3.2. Default Switch Settings x
3.2.1. Default Settings 3.2.2. Perform Board Restore through Quartus® Prime Programmer
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-board Clock through Clock Controller GUI 4.4. Monitor On-board Power through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The RAM Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab
A. Development Kits Components x
A.1. Board Overview A.2. Agilex™ 7 FPGA I-Series A.3. PCIe* and CXL Interfaces A.4. MCIO Connector A.5. MCIO Cable Assembly Information A.6. Network Interfaces A.7. Port Controller A.8. FPGA Configuration A.9. Supported Configuration Modes A.10. Memory Interfaces A.11. I2C A.12. Clock Circuits A.13. System Power A.14. Temperature Monitoring A.15. Mechanical Requirements A.16. Board Thermal Requirements A.17. Board Operating Conditions A.18. Over Temperature Warning LED
A.13. System Power x
A.13.1. Power Guidelines A.13.2. Power Distribution System A.13.3. Power Sequence A.13.4. Power Measurement
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Document Revision History for the Agilex™ 7 FPGA I-Series Development Kit User Guide
A. Development Kits Components
B. Additional Information

5. Revision History

Table 8.  Revision History of the Intel® Agilex™ I-Series FPGA Development Kit User Guide
Document Version Changes
2023.02.27 Updated the supported DDR4 speed for memory interfaces in the Feature Summary section.
2022.09.22
  • Added the Additional Information section.
  • Added The XCVR Tab section.
  • Added The QSFPDD PAM4 Tab section.
  • Added Figure: The QSFPDD PAM4 Tab.
  • Updated the Overview section.
  • Updated the Block Diagram section to include details about the CXL IP license.
  • Updated the About Intel® Quartus® Prime Software section.
  • Updated the section title from Perform Board Restore through Board Test System (BTS) GUI to Perform Board Restore through Intel® Quartus® Prime Programmer.
  • Updated the Download OpenJDK section.
  • Updated the Download OpenJFX section.
  • Updated the Install OpenJDK and OpenJFX section.
  • Updated The Sys Info Tab section.
  • Updated The QSFPDD NRZ Tab section.
  • Updated the Intel® Agilex™ I-Series FPGA section.
  • Updated the PCIe* and CXL Interfaces section.
  • Updated step 8 in the How to Generate a POF Image to Program the Flash section.
  • Updated the description of J6 and J7 in Table: Connectors on the Development Kit.
  • Updated the description of S2 and S3 in Table: Push-Buttons on the Development Kit.
  • Updated Figure: BTS GUI.
  • Updated Figure: OpenJDK Version.
  • Updated Figure: JavaFX Version.
  • Updated Figure: BTS Folder.
  • Updated Figure: Windows Console.
  • Updated Figure: Linux Console.
  • Updated Figure: The Configure Menu.
  • Updated Figure: The Sys Info Tab.
  • Updated Figure: The QSFPDD NRZ Tab.
  • Updated Figure: QSFPDD-PMA Setting.
  • Updated Figure: XCVR-Data Rate.
  • Updated Figure: The COMP-O Tab.
  • Updated Figure: The COMP-1 Tab.
  • Updated Figure: The DDR4-RDIMM Tab.
  • Updated Figure: Clock Controller GUI.
  • Updated Figure: Power Monitor GUI.
  • Removed Figure: Windows OpenJDK Version.
  • Removed Figure: Linux OpenJDK Version.
  • Removed support for Intel® Optane™ .
2022.03.30 Updated the MCIO Cable Assembly Information section.
2022.02.11
  • Added the Board Test System section.
  • Added the How to Generate a POF Image to Program the Flash section.
  • Added the How to Program the Generated POF Image section.
  • Added The Required SmartVID QSF Assignments to Compile a Design section.
  • Added Figure: SW1[1:4] Switch Setting.
  • Added Figure: SW2[1:4] Switch Setting.
  • Added Figure: SW3[1:4] Switch Setting.
  • Added Figure: SW4 Switch Setting.
  • Added Figure: SW5[1:4] Switch Setting.
  • Updated the PCIe* and CXL Interfaces section.
  • Updated Figure: Intel® Agilex™ I-Series FPGA Development Board Image—Front.
  • Updated the header of Table: Intel® Agilex™ I-Series FPGA Development Kit Ordering Information.
  • Updated Table: Factory Default Switch Settings.
  • Removed the Factory Reset section.
  • Minor editorial updates.
2021.11.17 Updated the PCIe* REFCLK Select function in the SW3[1:4] switch row in Table: Factory Default Switch Settings.
2021.09.24 Initial release.
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