F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath Avalon Memory-Mapped Interface 5.12. PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

6. IP Registers

You can access the CPRI registers for the F-Tile CPRI PHY Intel® FPGA IP core using the Avalon memory-mapped interface on each channel.
Table 29.  Address Ranges
Register Type Address Range
CPRI PHY Registers 0x0-0x3C
Table 30.  F-Tile CPRI PHY Registers
Address (Byte) Bit Name Description Access Reset
0x0 4 tx_cpri_fec_en Indicates whether the TX RSFEC block is enabled:
  • 0: disabled
  • 1: enabled

The TX datapath must be reset after changing this setting.

RW Power up value 2
3:0 tx_cpri_rate_sel Select the TX CPRI speed:
  • 1: 1.2G
  • 2: 2.4G
  • 3: 3G
  • 4: 4.9G
  • 5: 6G
  • 6: 9.8G
  • 9: 10G
  • 10: 12G
  • 11: 24G

The TX datapath must be reset after changing this setting.

RW Power up value 3
0x4 9:5 rx_bitslipboundary_sel Indicates number of bits that the 8b/10b RX PCS block slipped to achieve a deterministic latency. RO 0x0
4 rx_cpri_fec_en Indicates whether the RX RSFEC block is enabled:
  • 0: disabled
  • 1: enabled

The RX datapath must be reset after changing this setting.

RW Power up value2
3:0 rx_cpri_rate_sel Select the RX CPRI speed:
  • 1: 1.2G
  • 2: 2.4G
  • 3: 3G
  • 4: 4.9G
  • 5: 6G
  • 6: 9.8G
  • 9: 10G
  • 10: 12G
  • 11: 24G

The RX datapath must be reset after changing this setting.

RW Power up value3
0x8 31 tx_dl_restart Indicates the reset to allow TX deterministic latency (DL) measurements to be retaken:
  • 0: Reset disabled
  • 1: Reset enabled
 RW 0x0
30 rx_dl_restart Indicates the reset to allow RX deterministic latency (DL) measurements to be retaken:
  • 0: Reset disabled
  • 1: Reset enabled
 RW 0x0
1 tx_measure_valid Indicates whether the TX deterministic latency (DL) measurement values are valid:
  • 0: Invalid
  • 1: Valid
 RO 0x0
0 rx_measure_valid Indicates whether the RX deterministic latency (DL) measurement values are valid:
  • 0: Invalid
  • 1: Valid
Note: If block_lock is deasserted, this register is deasserted.
RO 0x0
0xC 20:0 tx_delay Indicates DL measurement values in fixed point format (Q13.8). TX datapath latency (in sampling_clk cycle).

Must be qualified with measure_valid.

RO 0x0
0x10 20:0 rx_delay Indicates DL measurement values in fixed point format (Q13.8). RX datapath latency (in sampling_clk cycle).

Must be qualified with measure_valid.

RO 0x0
0x14 3 tx_sync_valid Indicates whether TX synchronous counter values are valid:
  • 0: Invalid
  • 1: Valid
 RO 0x0
2 tx_async_valid Indicates whether TX asynchronous counter values are valid:
  • 0: Invalid
  • 1: Valid
 RO 0x0
1 rx_sync_valid Indicates whether RX synchronous counter values are valid:
  • 0: Invalid
  • 1: Valid
 RO 0x0
0 rx_async_valid Indicates whether RX asynchronous counter values are valid:
  • 0: Invalid
  • 1: Valid
 RO 0x0
0x18 19:0 tx_sync_counter TX sync counter value. Must be qualified with tx_sync_valid. RO 0x0
0x1C 19:0 tx_async_counter TX async counter value. Must be qualified with tx_async_valid. RO 0x0
0x20 19:0 rx_sync_counter RX sync counter value. Must be qualified with rx_sync_valid. RO 0x0
0x24 19:0 rx_async_counter RX async counter value. Must be qualified with rx_async_valid. RO 0x0
0x28 - 0x3C 31:0 Reserved. RO 0x0
2 For example, if power up is 24G with RSFEC, then reset value is 1.
3 For example, if power up is 24G with RSFEC, then reset value is 11 (0xb).
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