Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 9/26/2022
Public

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2.5.2.5. Finalize Stage Reports

The Finalize stage reports describe final placement and routing operations, including:
  • HSLP Summary. For Intel® Arria® 10 and Intel® Cyclone® 10 GX designs, the Compiler converts unnecessary tiles to High-Speed or Low-Power (HSLP) tiles.
  • Post-route hold fix-up data. For Intel® Stratix® 10 and Intel® Agilex™ designs, the Compiler reports hold violations for short paths following the Retime stage. The Fitter identifies and corrects the short paths with hold violations during the Fitter (Finalize) stage by adding routing wire along the paths.
Figure 54. Finalize Stage Reports ( Intel® Stratix® 10 Design)