50 Gbps Ethernet IP Core User Guide

ID 683158
Date 5/08/2017
Public
Document Table of Contents

4.1. 50GbE IP Core Functional Description

The Intel® FPGA 50GbE IP core implements an Ethernet MAC in accordance with the 25G & 50G Ethernet Specification . The IP core implements an Ethernet PCS and PMA (PHY) that handles the frame encapsulation and flow of data between a client logic and Ethernet network.

Figure 6.  50GbE IP Core MAC and PHY Clock Diagram

In the TX direction, the MAC assembles packets and sends them to the PHY. It completes the following tasks:

  • Accepts client frames
  • Inserts the inter-packet gap (IPG), preamble, start of frame delimiter (SFD), and padding

The PHY encodes MAC frames for reliable transmission over the media to the remote end.

In the RX direction, the PMA passes frames to the PCS that sends them to the MAC. The MAC completes the following tasks:

  • Performs CRC and malformed packet checks
  • Strips out the CRC, preamble, and SFD
  • Passes the remainder of the frame to the client

In preamble pass-through mode, the MAC passes on the preamble and SFD to the client instead of stripping them out. In RX CRC pass-through mode, the MAC passes on the CRC bytes to the client and asserts the end-of-packet signal in the same clock cycle as the final CRC byte.

Did you find the information on this page useful?

Characters remaining:

Feedback Message