Visible to Intel only — GUID: nik1411172550103
Ixiasoft
Product Discontinuance Notification
1. About the 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the 40GbE and 100GbE Link
A. 40-100GbE IP Core Example Design
B. Address Map Changes for the 40-100GbE IP Core v12.0 Release
C. 10GBASE-KR Registers
D. Additional Information
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 40-100GbE IP Core Parameters and Options
2.3. IP Core Parameters
2.4. Files Generated for the 40-100GbE IP Core
2.5. Simulating the IP Core
2.6. Integrating Your IP Core in Your Design
2.7. 40-100GbE IP Core Testbenches
2.8. Simulating the 40‑100GbE IP Core With the Testbenches
2.9. Compiling the Full Design and Programming the FPGA
2.10. Initializing the IP Core
3.2.1. IP Core TX Datapath
3.2.2. IP Core TX Data Bus Interfaces
3.2.3. 40-100GbE IP Core RX Datapath
3.2.4. IP Core RX Data Bus Interfaces
3.2.5. 40GbE Lower Rate 24.24 Gbps MAC and PHY
3.2.6. 100GbE CAUI–4 PHY
3.2.7. External Reconfiguration Controller
3.2.8. Congestion and Flow Control Using Pause Frames
3.2.9. Pause Control and Generation Interface
3.2.10. Pause Control Frame and Non‑Pause Control Frame Filtering and Forwarding
3.2.11. 40-100GbE IP Core Modes of Operation
3.2.12. Link Fault Signaling Interface
3.2.13. Statistics Counters Interface
3.2.14. MAC – PHY XLGMII or CGMII Interface
3.2.15. Lane to Lane Deskew Interface
3.2.16. PCS Test Pattern Generation and Test Pattern Check
3.2.17. Transceiver PHY Serial Data Interface
3.2.18. 40GBASE-KR4 IP Core Variations
3.2.19. Control and Status Interface
3.2.20. Clocks
3.2.21. Resets
3.2.2.1. 40-100GbE IP Core User Interface Data Bus
3.2.2.2. 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3.2.2.3. 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3.2.2.4. Bus Quantization Effects With Adapters
3.2.2.5. User Interface to Ethernet Transmission
3.2.3.1. 40-100GbE IP Core RX Filtering
3.2.3.2. 40-100GbE IP Core Preamble Processing
3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal
3.2.3.4. 40-100GbE IP Core CRC Checking
3.2.3.5. RX CRC Forwarding
3.2.3.6. RX Automatic Pad Removal Control
3.2.3.7. Address Checking
3.2.3.8. Inter-Packet Gap
3.2.3.9. Pause Ignore
3.2.4.1. 40-100GbE IP Core User Interface Data Bus
3.2.4.2. 40-100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface)
3.2.4.3. 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.4.4. 100GbE IP Core RX Client Interface Examples
3.2.4.5. Error Conditions on the RX Datapath
3.4.1.1. Transceiver PHY Control and Status Registers
3.4.1.2. Lock Status Registers
3.4.1.3. Bit Error Flag Registers
3.4.1.4. PCS Hardware Error Register
3.4.1.5. BER Monitor Register
3.4.1.6. Test Mode Register
3.4.1.7. Test Pattern Counter Register
3.4.1.8. Link Fault Signaling Registers
3.4.1.9. MAC and PHY Reset Registers
3.4.1.10. PCS‑VLANE Registers
3.4.1.11. PRBS Registers
3.4.1.12. 40GBASE-KR4 Registers
3.4.1.13. MAC Configuration and Filter Registers
3.4.1.14. Pause Registers
3.4.1.15. MAC Hardware Error Register
3.4.1.16. CRC Configuration Register
3.4.1.17. MAC Feature Configuration Registers
3.4.1.18. MAC Address Registers
3.4.1.19. Statistics Registers
Visible to Intel only — GUID: nik1411172550103
Ixiasoft
1.1. 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features
The 40- and 100-Gbps Ethernet MAC and PHY IP core offers the following features:
- Parameterizable through the IP Catalog available with the Quartus II software.
- Compliant with the IEEE 802.3ba-2010 High Speed Ethernet Standard available on the IEEE website (www.ieee.org).
- Soft PCS logic that interfaces seamlessly to Altera 10.3125 Gbps and 25.78125 Gbps serial transceivers.
- Standard XLAUI or CAUI external interface consisting of serial transceiver lanes operating at 10.3125 Gbps, or the CAUI-4 external interface consisting of four serial transceiver lanes operating at 25.78125 Gbps.
- Supports 40GBASE-R4, 100GBASE-R4, and 100GBASE-R10 PHY based on 64B/66B encoding with data striping and alignment markers to align data from multiple lanes.
- Supports 40GBASE-KR4 PHY and FEC option for interfacing to backplanes.
- Supports Synchronous Ethernet (Sync-E)
- Provides CDR recovered clock output signal to the device fabric.
- Optionally accepts two separate input reference clocks for the transmit and receive transceiver paths.
- Supports a lower–rate 40GbE option at 24.24 Gbps (4 x 6.25 Gbps line rate).
- Ethernet MAC supports the 40GbE or 100GbE line rate with a flexible and configurable feature set.
- Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
- Avalon-ST data path interface connects to client logic with the start of frame in the most significant byte (MSB) when optional adapters are used. Interface has data width 256 or 512 bits depending on the data rate.
- Optional custom streaming data path interface with narrower bus width and a start frame possible on 64‑bit word boundaries without the optional adapters. Interface has data width 128 or 320 bits depending on the data rate.
- MAC, PHY, or MAC and PHY options configurable at IP generation.
- TX only configuration options, RX only configuration options, and duplex configuration options; the 100GbE CAUI-4 option is available only in duplex mode.
- TX and RX CRC pass-through control.
- RX and TX preamble pass-through option for applications that require proprietary user management information transfer.
- TX automatic frame padding to meet the 64-byte minimum Ethernet frame length at the 40-100GbE Ethernet connection.
- Hardware and software reset control.
- TX MAC source address insertion control.
- One MAC address register for configurable RX destination address filtering.
- RX MAC padding removal control.
- Pause frame filtering control.
- Soft error detection on all internal RAMs for high reliability systems.
- RX FIFO in MAC provides cut-through or store-and-forward frame processing.
- Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average.
- Programmable IPG fine adjustment for Ethernet repeater/bump-in-the-wire applications and traffic shaping.
- Ethernet flow control using the pause registers or pause interface.
- Programmable maximum receive frame length up to 9600 bytes (jumbo frame) in store-and-forward mode; there is no frame size limitation for cut-through mode.
- Promiscuous (transparent) and non-promiscuous (filtered) operation modes or received frame address filtering.
- Configurable received frame filtering with cyclic redundancy check (CRC), runt, or oversized frame error.
- Optional statistics counters.
- Additional testbench logic to demonstrate Ethernet IP core behavior and customize the interface.
- Statistics real-time output counter increment signals vector.
- Fault signaling: detects and reports local fault and generates remote fault.
The 40-100GbE IP core can support full wire line speed with a 64-byte frame length and back-to-back or mixed length traffic, up to a programmable frame size greater than 9600 bytes, with no dropped packets.
For a detailed specification of the Ethernet protocol refer to the IEEE 802.3ba-2010 High Speed Ethernet Standard.
Related Information