100G Interlaken Design Example User Guide

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ID 683071
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for 100G Interlaken Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Example Design Behavior 2.5. Interface Signals 2.6. Register Map
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for 100G Interlaken Design Example User Guide

2.4. Example Design Behavior

Immediately following configuration on the Arria 10 device, when you type run_example_design in system console, the 100G Interlaken IP core hardware example design performs the following actions:

  1. Resets the 100G Interlaken IP core.
  2. Configures the 100G Interlaken IP core in internal loopback mode.
  3. Sends a sequence of 100 256-byte Interlaken packets with predefined data in the payload to the TX user data transfer interface of the IP core.
    Note: If the IP core is in dual segment mode, the hardware example design sends 65-byte bursts on the TX user data transfer interface. If the IP core is in single segment, Interleaved mode, the hardware example design sends 128-byte bursts.
  4. Checks the received packets and reports the status.

The packet checker included in the hardware example design provides the following basic packet checking capabilities:

  • Checks that the transmitted packet sequence is not violated
  • Checks that the received data matches expected values
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