Quartus® Prime Pro Edition User Guide: Programmer

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ID 683039
Date 4/09/2025
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Quartus® Prime Programmer User Guide 2. Using the Quartus® Prime Programmer 3. Using the HPS Flash Programmer A. Quartus® Prime Pro Edition User Guide: Programmer Document Archive B. Quartus® Prime Pro Edition User Guides
1. Quartus® Prime Programmer User Guide x
1.1. Generating Primary Device Programming Files 1.2. Generating Secondary Programming Files 1.3. Enabling Bitstream Security for Stratix® 10 and Agilex™ 7 Devices 1.4. Enabling Bitstream Encryption or Compression for Arria® 10 and Cyclone® 10 GX Devices 1.5. Generating Programming Files for Partial Reconfiguration 1.6. Generating Programming Files for Altera® FPGA Devices with Hard Processor Systems 1.7. Scripting Support 1.8. Generating Programming Files Revision History
1.1. Generating Primary Device Programming Files x
1.1.1. Specifying Voltage Regulator Options
1.2. Generating Secondary Programming Files x
1.2.1. Generating Secondary Programming Files (Programming File Generator) 1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) 1.2.3. Generating Secondary Programming Files (Settings: Programming Files Dialog Box)
1.2.1. Generating Secondary Programming Files (Programming File Generator) x
1.2.1.1. Configuration Modes (Programming File Generator) 1.2.1.2. Secondary Programming Files (Programming File Generator) 1.2.1.3. Differentiating Programming Bitstream Versions
1.2.2. Generating Secondary Programming Files (Convert Programming File Dialog Box) x
1.2.2.1. Secondary Programming Files (Convert Programming Files) 1.2.2.2. Configuration Modes (Convert Programming Files) 1.2.2.3. Debugging the Configuration (Convert Programming Files)
1.3. Enabling Bitstream Security for Stratix® 10 and Agilex™ 7 Devices x
1.3.1. Enabling Bitstream Authentication (Programming File Generator) 1.3.2. Specifying Additional Physical Security Settings (Programming File Generator) 1.3.3. Enabling Bitstream Encryption (Programming File Generator)
1.5. Generating Programming Files for Partial Reconfiguration x
1.5.1. Generating PR Bitstream Files 1.5.2. Partial Reconfiguration Bitstream Compatibility Checking 1.5.3. Raw Binary Programming File Byte Sequence Transmission Examples 1.5.4. Generating a Merged .pmsf File from Multiple .pmsf Files ( Arria® 10 and Cyclone® 10 GX Designs)
1.6. Generating Programming Files for Altera® FPGA Devices with Hard Processor Systems x
1.6.1. Generating Programming Files for HPS Boot First Boot Flows 1.6.2. Generating Programming Files for FPGA Configuration First Boot Flows
1.7. Scripting Support x
1.7.1. quartus_pfg Command Line Tool 1.7.2. quartus_cpf Command Line Tool
1.7.2. quartus_cpf Command Line Tool x
1.7.2.1. Generating a Partial-Mask SRAM Object File using a Mask Settings File and a SRAM Object File
2. Using the Quartus® Prime Programmer x
2.1. Quartus® Prime Programmer 2.2. Programming and Configuration Modes 2.3. Basic Device Configuration Steps 2.4. Specifying the Programming Hardware Setup 2.5. Programming with Flash Loaders 2.6. Verifying the Programming File Source with Project Hash 2.7. Using PR Bitstream Security Verification ( Stratix® 10 Designs) 2.8. Stand-Alone Programmer and Tools 2.9. Programmer Settings Reference 2.10. Scripting Support 2.11. Using the Quartus® Prime Programmer Revision History
2.4. Specifying the Programming Hardware Setup x
2.4.1. JTAG Chain Debugger Tool 2.4.2. Editing the Details of an Unknown Device 2.4.3. Running JTAG Daemon with Linux
2.4.1. JTAG Chain Debugger Tool x
2.4.1.1. JTAG Chain Integrity Tab 2.4.1.2. JTAG Chain Debugging Tab
2.5. Programming with Flash Loaders x
2.5.1. Specifying Flash Partitions 2.5.2. Full Erase of Flash Memory Sectors
2.6. Verifying the Programming File Source with Project Hash x
2.6.1. Obtaining Project Hash for Arria® 10 Devices
2.8. Stand-Alone Programmer and Tools x
2.8.1. Stand-Alone Programmer Memory Consumption
2.9. Programmer Settings Reference x
2.9.1. Device & Pin Options Dialog Box 2.9.2. More Security Options Dialog Box 2.9.3. Output Files Tab Settings (Programming File Generator) 2.9.4. Input Files Tab Settings (Programming File Generator) 2.9.5. Bitstream Co-Signing Security Settings (Programming File Generator) 2.9.6. Configuration Device Tab Settings 2.9.7. Add Partition Dialog Box (Programming File Generator) 2.9.8. Add Filesystem Dialog Box (Programming File Generator) 2.9.9. Convert Programming File Dialog Box 2.9.10. Compression and Encryption Settings (Convert Programming File) 2.9.11. SOF Data Properties Dialog Box (Convert Programming File) 2.9.12. Select Devices (Flash Loader) Dialog Box
2.10. Scripting Support x
2.10.1. The jtagconfig Debugging Tool
3. Using the HPS Flash Programmer x
3.1. Supported Devices 3.2. HPS Flash Programmer Command-Line Utility 3.3. How the HPS Flash Programmer Works 3.4. Using the Flash Programmer from the Command Line 3.5. Supported Memory Devices 3.6. HPS Flash Programmer User Guide Revision History
3.4. Using the Flash Programmer from the Command Line x
3.4.1. HPS Flash Programmer 3.4.2. HPS Flash Programmer Command Line Examples
Answers to Top FAQs
1. Quartus® Prime Programmer User Guide
2. Using the Quartus® Prime Programmer
3. Using the HPS Flash Programmer
A. Quartus® Prime Pro Edition User Guide: Programmer Document Archive
B. Quartus® Prime Pro Edition User Guides

1.1.1. Specifying Voltage Regulator Options

For Agilex™ FPGA portfolio devices only, you can specify the voltage source that monitors the voltage accuracy, including voltage regulators other than those listed as validated.

Follow these steps to specify voltage regulator options:

  1. Click Assignments > Device > Device & Pin Options. Device & Pin Options Dialog Box describes all options.
  2. Click Power Management & VID.
    Figure 4. Power Management & VID Report


  3. Click the More Options button. The Advanced Power Management & VID Options dialog box appears.
  4. To specify that the device queries the voltage regulator status via the STATUS REGISTER command, turn on Enable status_byte for polling (default setting).
    Figure 5. Advanced Power Management & VID Options


  5. To specify the source of the voltage regulator that verify the actual voltage against the voltage that you specify, specify the Voltage Regulator Source. The default setting is Voltage Regulator, which uses the voltage regulator. Alternatively, specify Internal VADC if the voltage reading comes from the FPGA internal VADC, or Omitted to perform no voltage reading.
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