‹ Back to Video Series: Parallel Programming and Optimization with Intel® Xeon Phi™ Coprocessors

Part 14: Example of Cache-Oblivious Recursion

We will discuss an approach to memory optimization based on recursive divide-and-conquer algorithm.

 

EPISODES (19)
NOW PLAYING

Part 1: Optimization Roadmap

(4:25)

NOW PLAYING

Part 2: Scalar Tuning and General Optimization

(10:04)

NOW PLAYING

Part 3: Optimization of Vectorization-Data Structures

(6:09)

NOW PLAYING

Part 4: Optimization of Vectorization-Alignment and Hints

(4:50)

NOW PLAYING

Part 5: Optimization of Vectorization: Regularizing Pattern

(9:35)

NOW PLAYING

Part 6: Strip-Mining for Vectorization

(6:15)

NOW PLAYING

Part 7: Vectorization Tuning Knobs

(2:54)

NOW PLAYING

Part 8: Optimization of Synchronization in Multithreaded Applications

(7:29)

NOW PLAYING

Part 9: Elimination of False Cache Line Sharing

(5:17)

NOW PLAYING

Part 10: Do You Have Enough Parallelism in Your Code?

(7:17)

NOW PLAYING

Part 11: Thread Affinity Control

(7:14)

NOW PLAYING

Part 12: Optimization of Memory Access

(7:15)

NOW PLAYING

Part 13: Example of Loop Tiling

(6:47)

NOW PLAYING

Part 14: Example of Cache-Oblivious Recursion

(5:36)

NOW PLAYING

Part 15: NUMA and Allocation on First Touch

(5:03)

NOW PLAYING

Part 16: Optimization of Communication: Offload

(6:57)

NOW PLAYING

Part 17: Optimization of Communication: MPI

(3:02)

NOW PLAYING

Part 18: Additional Topic-Load Balancing in Heterogeneous Systems

(5:50)

NOW PLAYING

Part 19: Closing Words

(1:39)

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.