‹ Back to Video Series: Parallel Programming and Optimization with Intel® Xeon Phi™ Coprocessors

Part 13: Example of Loop Tiling

In this episode, we will illustrate with an example the techniques for optimizing memory traffic by improving the temporal locality of data access. We will use loop tiling to improve the re-use of data in the matrix-vector multiplication problem.

 

EPISODES (19)
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Part 1: Optimization Roadmap

(4:25)

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Part 2: Scalar Tuning and General Optimization

(10:04)

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Part 3: Optimization of Vectorization-Data Structures

(6:09)

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Part 4: Optimization of Vectorization-Alignment and Hints

(4:50)

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Part 5: Optimization of Vectorization: Regularizing Pattern

(9:35)

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Part 6: Strip-Mining for Vectorization

(6:15)

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Part 7: Vectorization Tuning Knobs

(2:54)

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Part 8: Optimization of Synchronization in Multithreaded Applications

(7:29)

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Part 9: Elimination of False Cache Line Sharing

(5:17)

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Part 10: Do You Have Enough Parallelism in Your Code?

(7:17)

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Part 11: Thread Affinity Control

(7:14)

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Part 12: Optimization of Memory Access

(7:15)

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Part 13: Example of Loop Tiling

(6:47)

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Part 14: Example of Cache-Oblivious Recursion

(5:36)

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Part 15: NUMA and Allocation on First Touch

(5:03)

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Part 16: Optimization of Communication: Offload

(6:57)

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Part 17: Optimization of Communication: MPI

(3:02)

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Part 18: Additional Topic-Load Balancing in Heterogeneous Systems

(5:50)

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Part 19: Closing Words

(1:39)

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.