‹ Back to Video Series: Parallel Programming and Optimization with Intel® Xeon Phi™ Coprocessors

Part 1: SIMD Parallelism and Intrinsics

In the previous lectures, we already discussed the purpose and the architecture of Intel® Xeon Phi™ coprocessors. After that, we studied programming models for Intel Xeon Phi coprocessors: native and offload. Now we are beginning a new chapter, number 4, titled "Expressing Parallelism". In this chapter, our goal is to learn how to express data parallelism, thread parallelism and process parallelism in applications for Intel Xeon processors and Xeon Phi coprocessors.

 

EPISODES (9)
NOW PLAYING

Part 1: SIMD Parallelism and Intrinsics

(6:02)

NOW PLAYING

Part 2: Automatic Vectorization and Array Notation

(6:52)

NOW PLAYING

Part 3: Vector Dependence, Pointer Disambiguation, and SIMD-Enabled Functions

(8:45)

NOW PLAYING

Part 4: Thread Parallelism and OpenMP*

(3:43)

NOW PLAYING

Part 5: Parallel Loops, Private and Shared Variables, Scheduling

(4:33)

NOW PLAYING

Part 6: Fork-Join Model OpenMP* Tasks

(3:20)

NOW PLAYING

Part 7: Race Conditions and Mutexes

(6:41)

NOW PLAYING

Part 8: Parallel Reduction

(4:36)

NOW PLAYING

Part 9: Distributed-Memory Parallelism and MPI

(6:49)

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.