oneAPI Software Abstraction for Heterogeneous Computing: Part 2
The oneAPI platform is a cross-industry, open, standards-based unified programming model. The oneAPI specification extends existing developer programming models to enable a diverse set of hardware through language, a set of library APIs, and a low-level hardware interface to support cross-architecture programming. It builds upon industry standards and provides an open, cross-platform developer stack to improve productivity and innovation.
At the core of the oneAPI platform is the Data Parallel C++ (DPC++) programming language, which builds on the International Organization for Standardization (ISO) C++ and Khronos* SYCL* standards. DPC++ provides explicit parallel constructs and offload interfaces to support a broad range of accelerators. In addition to DPC++, the oneAPI platform provides libraries for compute- and data-intensive domains, such as deep learning, scientific computing, video analytics, and media processing. Finally, a low-level hardware interface defines a set of capabilities and services to allow a language runtime system to effectively utilize a hardware accelerator.
Sujata Tibrewala is manager of the oneAPI platform worldwide developer community at Intel. She defines programs to enable the developer community to use the oneAPI platform. She is a co-chair for the Institute of Electrical and Electronics Engineers (IEEE) Edge Automation Platform roadmap and is a frequent presenter at various IEEE and industry conferences. She has held the positions of director at Silicon Valley Engineering Council and chair of the Technical Steering Committee for documentation for Akraino. She is also a self-taught artist who has exhibited at various venues in the United States and India, including the University of Illinois Chicago, Life Force Arts Center, Lalit Kala Academy, and others.
Zheming Jin finished his PhD in computer science and engineering at University of South Carolina, where his research focused on program synthesis and applications development targeting field-programmable gate arrays (FPGAs). As a postdoctoral appointee at Argonne National Laboratory, he evaluated high-level synthesis and the oneAPI tool on FPGAs and GPUs, respectively. His current work with the oneAPI platform is to develop programs for the development of SYCL compilers.
Aksel Alpay is a researcher and software engineer from Heidelberg University where he works on high-performance computing topics. In particular, he is the creator and lead developer of the hipSYCL SYCL implementation and also engages within the Khronos SYCL working group to advance the language.
Kumudha Narasimhan is a senior software engineer at Codeplay*. Her work focuses on optimizing compilers and middleware to provide performance and portability on various heterogeneous compute systems. She joined Codeplay in 2019 and has worked on many projects in this space. They include adding the NVIDIA* back end for oneAPI Math Kernel Library (oneMKL) and oneAPI Deep Neural Network Library (oneDNN) and optimizing various neural networks using the Glow compiler for proprietary custom hardware. She presently leads the team that focuses on optimizing AI and deep neural network (DNN) computations for different architectures. She received her master's degree in computer science from Indian Institute of Science, where she worked on a domain-specific language to optimize linear algebra computations and multigrid methods using polyhedral compilation techniques.
Ronan Keryell is principal software engineer at Xilinx* Research Labs. He works on SYCL C++-based programming models for heterogeneous systems like FPGAs and coarse-grained reconfigurable architectures (CGRA). He is the specification editor of the SYCL standard and member of the SYCL, Standard Portable Intermediate Representation (SPIR), and the OpenCL™ program standards committees from Khronos Group and the ISO C++ committee. He received a Master of Science degree in electrical engineering. He earned his PhD in computer science in 1992 from École Normale Supérieure of Paris and University of Paris Sud on the design of a massively parallel Reduced Instruction Set Computer (RISC)-based Very Long Instruction Word– Single Instruction Multiple Data (VLIW-SIMD) graphics computer and its programming environment.
James Reinders is an engineer at Intel focused on enabling parallel programming in a heterogeneous world. He has helped create 10 technical books related to parallel programming. His latest book is about SYCL and is a free download. He has helped to make key contributions to two of the world's fastest computers and many other supercomputers and software developer tools.
Product and Performance Information
Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.