User Guide


Flags Merge Stalls

Metric Description

Some instructions have increased latency on Intel microarchitecture code name Sandy Bridge. Shift cl operations require a potentially expensive flag merge. This metric estimates the performance penalty of that merge.

Possible Issues

A significant proportion of cycles were spent handling flags merge operations. Use the source view to discover the responsible instructions and try to avoid their use.

Product and Performance Information


Performance varies by use, configuration and other factors. Learn more at