Analyze Platform Performance
- Analyze platform I/O traffic on per-I/O-device basis, whether the I/O device is an external PCIe device or an integrated accelerator.
- Analyze efficiency of Intel® Data Direct I/O technology (Intel® DDIO) utilization.
- Analyze Intel® Virtualization Technology for Directed I/O (Intel® VT-d) utilization.
- Monitor DRAM and persistent memory bandwidth consumption.
- Identify I/O performance issues potentially caused by inefficient remote socket accesses.
- Identify sources of outbound I/O (MMIO) traffic.
Analyze Topology and Hardware Resource Utilization
Analyze Platform I/O Bandwidth
- Inbound PCIe Bandwidthis induced by I/O devices—whether external PCIe devices and/or integrated accelerators—that write to and read from the system memory. These reads and writes are processed by the platform through the Intel® Data Direct I/O (Intel® DDIO) feature.
- Inbound PCIe Read— the I/O device reads from the platform memory.
- Inbound PCIe Write— the I/O device writes to the platform memory.
- Outbound PCIe Bandwidthis induced by core transactions targeting the memory or registers of the I/O device. Typically, the core accesses the device memory through the Memory-Mapped I/O (MMIO) address space.
- Outbound PCIe Read— the core reads from the registers of the device.
- Outbound PCIe Write— the core writes to the registers of the device.
- TheInbound PCIe Bandwidthmetrics are only available for server platforms based on Intel® microarchitecture code named Sandy Bridge EP and newer.
- TheOutbound PCIe Bandwidthmetrics are only available for server platforms based on Intel® microarchitecture code named Haswell EP and newer.
Analyze Efficiency of Intel® Data Direct I/O Utilization
Analyze Utilization of Intel® Virtualization Technology for Directed I/O
- Average IOTLB Miss Penalty, ns— average amount of time spent on handling an IOTLB miss. Includes looking up the context cache, intermediate page table caches and page table reads (page walks) on a miss, which turn into memory read requests.
- Memory Accesses Per IOTLB Miss— average number of memory read requests (page walks) per IOTLB miss.
Analyze MMIO Access
- This feature is only available starting with server platforms based on the Intel® microarchitecture code name Skylake.
- OnlyAttach to ProcessandLaunch Applicationcollection modes are supported. When running in theProfile Systemmode, this option only reveals functions performing reads from uncacheable memory.
Analyze Memory, Persistent Memory, and Cross-Socket Bandwidth
- UPI Utilization Outgoing– ratio metric that shows UPI utilization in terms of transmit.
- UPI Bandwidth– shows detailed bandwidth information with breakdown by data/non-data.