Analyze Platform Performance
- PCIe and platform-level IO traffic
- DRAM Bandwidth
- Intel® Ultra Path Interconnect (Intel® UPI) Utilization
- Analyze PCIe traffic
- Monitor DRAM bandwidth consumption
- Identify I/O performance issues potentially caused by inefficient remote socket accesses
- Identify sources of Outbound PCIe traffic
Analyze Topology and Device Utilization
Analyze PCIe Traffic
- Inbound PCIe Bandwidthis induced by PCIe devices that write and read to and from the system memory. These metrics are only available for server platforms based on the Intel® microarchitecture code named Sandy Bridge EP and later.
- Inbound PCIe Read— the PCIe device reads from the platform memory.
- Inbound PCIe Write— the PCIe device writes to the platform memory.
- Outbound PCIe Bandwidthis induced by core transactions targeting the memory or registers of the PCIe device. Typically, the core accesses the device memory through the Memory-Mapped I/O (MMIO) address space. These metrics are only available for server platforms based on the Intel® microarchitecture code named Broadwell EP and later.
- Outbound PCIe Read— the core reads from the registers of the device.
- Outbound PCIe Write— the core writes to the registers of the device.
Analyze Efficiency of Intel® Data Direct I/O Utilization
Analyze MMIO Access
- This feature is only available starting with server platforms based on the Intel® microarchitecture code name Skylake.
- OnlyAttach to ProcessandLaunch Applicationcollection modes are supported.
Analyze Memory and Cross-Socket Bandwidth
- UPI Utilization Outgoing– ratio metric that shows UPI utilization in terms of transmit.
- UPI Bandwidth– shows detailed bandwidth information with breakdown by data/non-data.