INGREDIENTS
DIRECTIONS:
Run Memory Access analysis
Locate Cache Misses
Use CAT to Reorganize Cache Segments Between Cores

Ingredients

Application:
A real-time application (RTA) with an allocated buffer that fits into Last Level Cache (LLC). The RTA reads from this buffer continuously.
RTAs are programs that function within a time frame specified by the user as immediate or current. Real-time programs must guarantee a response within specified time constraints, also known as "deadlines". There can be several reasons for missing a deadline:
Preemptions
Interrupts
An unexpected latency in the critical code execution
A Real-Time Operating System (RTOS) provides effective solutions to isolate an application to avoid its preemptions and interrupts. However, latency can still result from CPU Microarchitecture issues, like a CPU cache miss penalty. Here is an example of an RTA:
struct timespec sleep_timeout =
     (struct timespec) { .tv_sec = 0, .tv_nsec = 10000000 };
...
buffer=malloc(128*1024);
...
run_workload(buffer,128*1024);
void run_workload(void *start_addr,size_t size) {
unsigned long long i,j;
for (i=0;i<1000;i++)
{
     nanosleep(&sleep_timeout,NULL);
     for (j=0;j<size;j+=32)
     {
        asm volatile("mov(%0,%1,1),%%eax"
            :
        :"r" (start_addr),"r"(i)
            :"%eax","memory");
     }
}
}

    
'Noisy Neighbors' Application:
A stress-ng tool to load and stress a cache.
Tools:
Intel® VTune™
Profiler
- Memory Access Analysis. Set
AMPLXE_EXPERIMENTAL=cat
to enable the
Cache Availability (preview)
feature.
Starting with the 2020 release, Intel® VTune™ Amplifier has been renamed to
Intel® VTune™
Profiler
.
Most recipes in the
Intel® VTune™
Profiler
Performance Analysis Cookbook are flexible. You can apply them to different versions of
Intel® VTune™
Profiler
. In some cases, minor adjustments may be required.
Get the latest version of
Intel® VTune™
Profiler
:
From the
Intel® VTune™
Profiler
product page.
Download the latest standalone package from the Intel® oneAPI standalone components page.
Operating system:
Linux* OS
Hardware:
Intel Atom® Processor E3900 Series (code named Apollo Lake) Leaf Hill with L2 CAT capabilities enabled.

Run Memory Access Analysis

stress-ng -C 10 --cache-level 2 --taskset 2 --aggressive -v --metrics-brief

Locate Cache Misses

Use CAT to Reorganize Cache Segments Between Cores

Configure the MSRs directly. See Section 17.19 of the Intel® 64 and IA-32 Architectures Software Developer's Manual (Volume 3B).
Use Resource Control (resctrl) - A kernel interface for CPU Resource Allocation.

#set '00000001' Capacity Bit Mask for CORE 3
mkdir /sys/fs/resctrl/clos0
echo 8 > /sys/fs/resctrl/clos0/cpus
echo 'L2:1=1' > /sys/fs/resctrl/clos0/schemata
#set '11111110' CBM for rest CORE
echo 'L2:1=fe' > /sys/fs/resctrl/schemata

#set '00001111' Capacity Bit Mask for CORE 3
mkdir /sys/fs/resctrl/clos0
echo 8 > /sys/fs/resctrl/clos0/cpus
echo 'L2:1=f' > /sys/fs/resctrl/clos0/schemata
#set '11110000' CBM for rest CORE
echo 'L2:1=f0' > /sys/fs/resctrl/schemata

#Create the pseudo-locked region with 1 cache segment
mkdir /sys/fs/resctrl/demolock
echo pseudo-locksetup > /sys/fs/resctrl/demolock/mode
echo 'L2:1=0X1' > /sys/fs/resctrl/demolock/schemata
cat /sys/fs/resctrl/demolock/mode
pseudo-locked

struct timespec sleep_timeout =
     (struct timespec) { .tv_sec = 0, .tv_nsec = 10000000 };
...
/* buffer=malloc(128*1024); */
open("/dev/pseudo_lock/demolock",0_RDWR);
buffer=mmap(0,128*1024,PROT_READ|PROT_WRITE,MAP_SHARED,dev_fd,0);
...
run_workload(buffer,128*1024);
void run_workload(void *start_addr,size_t size) {
unsigned long long i,j;
for (i=0;i<1000;i++)
{
     nanosleep(&sleep_timeout,NULL);
     for (j=0;j<size;j+=32)
     {
        asm volatile("mov(%0,%1,1),%%eax"
            :
        :"r" (start_addr),"r"(i)
            :"%eax","memory");
     }
}
}