- From your host system, connect to the target system:ssh <user>@<target>
- In the SSH session, copy the UEFI binary of the real-time readiness checker to the boot partition to make it accessible from the UEFI shell:cp /usr/share/tcc_tools/tools/tcc_rt_checker.efi /boot/efi/EFI/BOOT/
- Reboot the target system and enter the UEFI/BIOS. Go toBoot Manager Menu > Internal UEFI Shell.
- Inputmapto explore the list of available partitions:map
- Navigate to the “boot” partition from the shell, using eitherfs0orfs1:fs0:The partitionsfs0andfs1are subject to change and depend on the BIOS/UEFI version. When both options are available, usefs1.
- Go to the real-time readiness checker:cd EFI cd BOOT
- Run the tool:tcc_rt_checker.efi
- To scroll up and down, pressSHIFT + Page Up/Page Down, respectively.
- First, the tool verifies that the device has a supported processor. If the tool detects an unsupported processor, it stops without performing the remaining checks.
- If the tool detects a supported processor, it completes all checks and prints the results. Review the Result column for each checker. Possible results are as follows:
- RT_READY: The target system has the optimal configuration for real-time applications.
- NON_RT_READY: The target system does not have the optimal configuration.
- FAILED: The checker failed.
Command-Line Options: UEFI Version
usage: tcc_rt_checker [-h] [-l]
Optional. Show this help message and exit.
Optional. Details about “NOT RT READY” and “FAILED” results.
Report Description: UEFI Version
- Processor Checker
- Intel® TCC Tools Checkers
- Real-Time BIOS Capabilities Checkers
Checks for the presence of a real-time CPU model.
Cache Allocation Technology
Checks whether the CPU supports Cache Allocation Technology (CAT). The fundamental goal of Cache Allocation Technology is to enable resource allocation based on application priority or Class of Service (COS). The processor exposes a set of Classes of Service into which applications (or individual threads) can be assigned. Cache allocation for the respective applications or threads is then restricted based on the class with which they are associated. By assigning different classes to real-time and non-real-time applications, cache access interference from non-real-time applications is eliminated. In addition, CAT is foundational for software SRAM functionality.
Cache Allocation Technology capabilities
Checks the CAT capabilities of the CPU.
Checks SMI counter changes on reading UEFI runtime variables.
Intel® Hyper-Threading Technology
Verifies that Intel® Hyper-Threading Technology (Intel® HT Technology) is disabled or unsupported by the CPU. Hyper-Threading can cause latency as you can only swap threads on instruction boundaries, so a real-time thread can be stalled by a long instruction running on the other logical thread on that core.
Enhanced Intel SpeedStep® Technology
Checks the status of Enhanced Intel SpeedStep® Technology (P-states). For Intel Atom® x6000E Series Processors, 11th Generation Intel® Core™ Processors, Intel® Xeon® W-11000E Series Processors the expected state is disabled. P-states are the various execution power states of the processor. These are the frequency-voltage pairs that dictate the speed at which the processor will run. P-states transitions introduce latencies for real-time applications because of the time it takes to transition between frequencies.
#AC Split Lock
Checks whether Alignment Check is enabled. Split locks are atomic instructions (either explicitly via the LOCK prefix, or implicit, i.e., XCHG) whose operand is split across a cache line boundary. Split locks result in the lock transaction being split across two cache lines forcing a bus lock. The bus lock prevents any other cores or I/O devices from initiating any transactions for the duration of the atomic transaction’s read-modify-write flow. As the system must complete current transactions in flight before the bus lock can be acquired, the jitter introduced by a bus lock can be significant (10s of microseconds). The #AC on Split Lock feature prevents the system from taking a bus lock because of a split lock. This enforcement is achieved by hardware throwing the #AC exception whenever a split lock is encountered, resulting in the offending process being terminated.
Because of the presence of split locks in the bootloader (GRUB) included in the board support package (BSP), the BIOS does not include this feature in Intel® TCC Mode, and this checker is always considered RT_READY.
CPU PCI Express* ASPM
Checks whether Active State Power Management (ASPM) is disabled. ASPM is an autonomous hardware-based, active state mechanism that enables power savings even when the connected components are in the D0 state. After a period of idle link time, an ASPM Physical-Layer protocol places the idle link into a lower power state. ASPM causes latency because of the delay for a device to wake from a low power state.
Intel® Speed Shift Technology
Checks the status of Intel® Speed Shift Technology. For Intel Atom® x6000E Series Processors, 11th Generation Intel® Core™ Processors, Intel® Xeon® W-11000E Series Processors the expected state is disabled. Intel® Speed Shift Technology lets the hardware switch P-States, which causes latency because of the time it takes to transition between frequencies.