About the Sample
TGPIO enables you to generate a periodic signal with a given frequency, but not every arbitrary frequency can be generated exactly because of limitations of the internal clock frequency.
For example, 11th Gen Intel® Core™ processors have an internal ART clock with a 24-MHz frequency, but the target frequency is 13 kHz. TGPIO cannot generate exactly the same signal because the target period is not a multiple of the ART clock period. The closest possible frequencies are about 13,001 Hz and 12,994 Hz. However, you can use the software to change the period periodically, to generate a signal with an average frequency of 13 kHz and the phase error as small as possible.
This sample demonstrates how to achieve the closest possible signal by measuring the real signal period and using a proportional integral (PI) controller to adjust the signal period.
How the Sample Works
This sample performs the following actions to generate a signal as close as possible to the required signal:
The following time diagram explains the sample and calculations.
Given the start timestamp 
, the sample enables a TGPIO periodic signal with a given expected period 
. The sample sleeps for some time and then measures the number of edges of the real signal 
and the timestamp of the last edge 
.
, the sample enables a TGPIO periodic signal with a given expected period . The sample sleeps for some time and then measures the number of edges of the real signal and the timestamp of the last edge .Phase error calculation
The timestamp 
of the corresponding -th edge of the expected signal is:
of the corresponding -th edge of the expected signal is:
= 
+ 
* 
Phase (integral) error is the difference between expected and real timestamps of the corresponding 
-th edge:
-th edge:
Period error calculation
The measured half-period 
of the real signal is:
of the real signal is: = 
PI controller and period adjustment
The sample calculates period adjustment using a PI controller:
= 
+ 
where 
is the proportional gain of the controller, and 
is the integral gain of the controller.
is the proportional gain of the controller, and is the integral gain of the controller.The sample uses this adjustment to change the signal period:
= 
+ 
This value is fed to the TGPIO to generate a signal for the next interval
= . The start time of the new signal generation is:
= . The start time of the new signal generation is:
= + 
This sample demonstrates frequency generation relative to the ART clock. If you need frequency generation relative to the system clock (for example, CLOCK_REALTIME), convert the ART time to system time using cross-timestamping. Refer to Basic Time-Aware GPIO (TGPIO) Samples and Advanced Time-Aware GPIO (TGPIO) Sample for cross-timestamping example code.