Data Streams Supported
The data streams optimizer tunes the platform to meet specified
requirements for the following data streams. This table provides a short description of each stream and links to more information in subsequent sections.
Data Stream | Description |
|---|---|
A PCIe device is reading data from a memory buffer. | |
A PCIe device is writing data to a memory buffer. | |
A processor core is reading data from a PCIe endpoint. | |
A processor core responds to a message signaled interrupt (MSI) generated by a PCIe endpoint. In this guide, the term message signaled interrupt or MSI is used generically to cover both MSI and MSI-X. | |
A processor core is writing data to a memory-mapped I/O (MMIO) space region on a PCIe device. |
PCIe from Memory (Reads)
The PCIe-from-memory stream refers to when a PCIe endpoint issues a read
request to memory and a completion is generated back to the endpoint
once the requested data has been retrieved. The latency of this stream
is measured from the time when a PCIe read request is issued on the PCIe
link targeting a data buffer in memory to when the PCIe completion with
data is sent on the PCIe link.
PCIe to Memory (Writes)
The PCIe-to-memory stream refers to when a PCIe posted write with data
is issued by a PCIe endpoint to when it arrives at memory. The
PCIe-to-memory stream latency is estimated to be equivalent to half of
the PCIe-from-memory stream latency.
Core from PCIe (MMIO Reads)
The core-from-PCIe stream for memory-mapped I/O (MMIO) reads refers to when the core generates a read request to the PCIe endpoint’s MMIO address space and
then a completion with requested data is sent back to the core. The
latency of this stream is measured from the time it takes the processor
core to perform a load from the MMIO address space on a PCIe endpoint to
the time at which the core receives a completion with the requested
data. The latency depends on the overhead from the endpoint. This
overhead, or turnaround time of the endpoint, is the time it takes for
an inbound MMIO read request to be serviced by the endpoint and then
returned to the PCIe link. Internal logic in the endpoint contributes to
how quickly read request completion is returned to the PCIe link. When
optimizing for the core-from-PCIe stream latency, the turnaround time of
the endpoint should be comprehended.
Core from PCIe (PCIe MSI)
The core-from-PCIe stream for PCIe message-signaled interrupts (MSIs)
refers to MSIs generated by a PCIe endpoint and serviced by the
processor core via the interrupt service routine (ISR). The latency of
this stream begins when the interrupt is triggered and ends when the
endpoint is notified of the ISR completing execution.
In this guide, the term
message signaled interrupt
or MSI
is used generically to cover both MSI and MSI-X.
Core to PCIe (MMIO Writes)
The core-to-PCIe stream refers to when a processor core generates a
posted write request to the PCIe endpoint’s MMIO address space. The
latency of this stream is estimated to be equivalent to half the
core-from-PCIe (MMIO reads) stream latency.
